Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

[Simon Wright <simon@symple.nz>]

Tested on R76S (RK3576) + LG G3 OLED at 1920x1080@60 bpc=10
(tmds_char_rate = 185625000): phy_configure / phy_power_on /
atomic_enable consistent end-to-end, no rate recalculation drift.
Matches the cover letter behaviour.

Heiko, Vinod -- any chance the series can be applied?

Tested-by: Simon Wright <simon@symple.nz>

Regards,
Simon
Symple Solutions, Dunedin, New Zealand

On 28/02/2026 9:48 am, Cristian Ciocaltea wrote:
> This series provides a set of bug fixes and cleanups for the Rockchip
> Samsung HDPTX PHY driver.
>
> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> calculation and synchronization issues.  Specifically, it fixes edge
> cases where the PHY PLL is pre-programmed by an external component (like
> a bootloader) or when changing the color depth (bpc) while keeping the
> modeline constant.  Because the Common Clock Framework .set_rate()
> callback might not be invoked if the pixel clock remains unchanged, this
> previously led to out-of-sync states between CCF and the actual HDMI PHY
> configuration.
>
> The second part focuses on code cleanups and modernizing the register
> access.  Now that dw_hdmi_qp driver has fully switched to using
> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> and the restrict_rate_change flag logic.  Finally, it refactors the
> driver to consistently use standard bitfield macros.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> Cristian Ciocaltea (6):
>        phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
>        phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
>        phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
>        phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
>        phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
>        phy: rockchip: samsung-hdptx: Consistently use bitfield macros
>
>   drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 215 +++++++++-------------
>   1 file changed, 92 insertions(+), 123 deletions(-)
> ---
> base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
> change-id: 20260227-hdptx-clk-fixes-47426632f862
>
>
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> From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> Subject: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API
>   transition cleanups
> Date: Fri, 27 Feb 2026 22:48:44 +0200
> Message-Id: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com>
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> X-Change-ID: 20260227-hdptx-clk-fixes-47426632f862
> To: Vinod Koul <vkoul@kernel.org>,
>   Neil Armstrong <neil.armstrong@linaro.org>,
>   Heiko Stuebner <heiko@sntech.de>, Algea Cao <algea.cao@rock-chips.com>,
>   Dmitry Baryshkov <lumag@kernel.org>
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> This series provides a set of bug fixes and cleanups for the Rockchip
> Samsung HDPTX PHY driver.
>
> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> calculation and synchronization issues.  Specifically, it fixes edge
> cases where the PHY PLL is pre-programmed by an external component (like
> a bootloader) or when changing the color depth (bpc) while keeping the
> modeline constant.  Because the Common Clock Framework .set_rate()
> callback might not be invoked if the pixel clock remains unchanged, this
> previously led to out-of-sync states between CCF and the actual HDMI PHY
> configuration.
>
> The second part focuses on code cleanups and modernizing the register
> access.  Now that dw_hdmi_qp driver has fully switched to using
> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> and the restrict_rate_change flag logic.  Finally, it refactors the
> driver to consistently use standard bitfield macros.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> Cristian Ciocaltea (6):
>        phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
>        phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
>        phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
>        phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
>        phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
>        phy: rockchip: samsung-hdptx: Consistently use bitfield macros
>
>   drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 215 +++++++++-------------
>   1 file changed, 92 insertions(+), 123 deletions(-)
> ---
> base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
> change-id: 20260227-hdptx-clk-fixes-47426632f862
>
>
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> From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> Subject: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API
>   transition cleanups
> Date: Fri, 27 Feb 2026 22:48:44 +0200
> Message-Id: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com>
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> X-Change-ID: 20260227-hdptx-clk-fixes-47426632f862
> To: Vinod Koul <vkoul@kernel.org>,
>   Neil Armstrong <neil.armstrong@linaro.org>,
>   Heiko Stuebner <heiko@sntech.de>, Algea Cao <algea.cao@rock-chips.com>,
>   Dmitry Baryshkov <lumag@kernel.org>
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>
> This series provides a set of bug fixes and cleanups for the Rockchip
> Samsung HDPTX PHY driver.
>
> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> calculation and synchronization issues.  Specifically, it fixes edge
> cases where the PHY PLL is pre-programmed by an external component (like
> a bootloader) or when changing the color depth (bpc) while keeping the
> modeline constant.  Because the Common Clock Framework .set_rate()
> callback might not be invoked if the pixel clock remains unchanged, this
> previously led to out-of-sync states between CCF and the actual HDMI PHY
> configuration.
>
> The second part focuses on code cleanups and modernizing the register
> access.  Now that dw_hdmi_qp driver has fully switched to using
> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> and the restrict_rate_change flag logic.  Finally, it refactors the
> driver to consistently use standard bitfield macros.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> Cristian Ciocaltea (6):
>        phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
>        phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
>        phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
>        phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
>        phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
>        phy: rockchip: samsung-hdptx: Consistently use bitfield macros
>
>   drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 215 +++++++++-------------
>   1 file changed, 92 insertions(+), 123 deletions(-)
> ---
> base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
> change-id: 20260227-hdptx-clk-fixes-47426632f862
>
>

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