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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=michael.riesch@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1785755053; s=zohomail; d=collabora.com; i=michael.riesch@collabora.com; h=Message-ID:Date:Date:MIME-Version:Subject:Subject:To:To:Cc:Cc:From:From:In-Reply-To:Content-Type:Content-Transfer-Encoding:Message-Id:Reply-To; bh=vEjfuOOqjt4DKH+Agnkv8+PSzwehlSi9y606REMac8k=; b=YmslsaxG4pGR0uRF+wFiDwdG+68+XDpe+xbWRA4G5/fEC/yC73+yew9Z3yc40h1r 7fiV9ZV8CoN5NjdzRpZOupXOJ4zRUOr4w5BpzlxMnGvxFPQJfxPac1ySZ3QVXg/zasg peZnfCqRls+GmQbtS0GojJ4U75BGM13gKde5pvfU= Received: by mx.zohomail.com with SMTPS id 1785755051075901.122732738344; Mon, 3 Aug 2026 04:04:11 -0700 (PDT) Message-ID: Date: Mon, 3 Aug 2026 13:04:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/3] phy: rockchip: phy-rockchip-inno-csidphy: add clock lane phase tuning To: Gerald Loacker , Vinod Koul , Neil Armstrong , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260725-feature-mipi-csi-dphy-4k60-v4-0-5b2c4626d31e@wolfvision.net> <20260725-feature-mipi-csi-dphy-4k60-v4-3-5b2c4626d31e@wolfvision.net> Content-Language: en-US From: Michael Riesch In-Reply-To: <20260725-feature-mipi-csi-dphy-4k60-v4-3-5b2c4626d31e@wolfvision.net> X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260803_040421_891411_ED3E5D00 X-CRM114-Status: GOOD ( 20.31 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hi Gerald, On 7/25/26 18:56, Gerald Loacker wrote: > At high data rates like 4K60 (2500 Mbps), such as when using an > LT6911GXD bridge chip on an RK3588 board, fixed default timing parameters > can cause signal integrity issues and clock-data recovery failures. > The driver currently lacks a mechanism to adjust the clock lane sampling > phase to compensate for board-specific trace variations. > > Resolve this by parsing and applying the optional 'rockchip,clk-lane-phase' > device tree property. This enables board-specific tuning of the clock > lane sampling phase in ~40 ps steps (range 0-7) to optimize link > stability. If the property is absent, the driver falls back to the > hardware default. > > Signed-off-by: Gerald Loacker Reviewed-by: Michael Riesch Thanks and best regards, Michael > --- > drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 25 ++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c > index 5281f8dea0ad3..d989f1649b0e4 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c > @@ -69,6 +69,10 @@ > #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 > #define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 > > +#define CSIDPHY_LANE_CLK_3_PHASE 0x38 > +#define CSIDPHY_CLK_PHASE_MASK GENMASK(6, 4) > +#define CSIDPHY_CLK_PHASE_DEFAULT 3 > + > #define RESETS_MAX 2 > > /* > @@ -151,6 +155,7 @@ struct rockchip_inno_csidphy { > const struct dphy_drv_data *drv_data; > struct phy_configure_opts_mipi_dphy config; > u8 hsfreq; > + int clk_phase; > }; > > static inline void write_grf_reg(struct rockchip_inno_csidphy *priv, > @@ -304,6 +309,13 @@ static int rockchip_inno_csidphy_power_on(struct phy *phy) > rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq, > CSIDPHY_LANE_THS_SETTLE(i)); > > + if (priv->clk_phase >= 0) { > + val = readl(priv->phy_base + CSIDPHY_LANE_CLK_3_PHASE); > + val &= ~CSIDPHY_CLK_PHASE_MASK; > + val |= FIELD_PREP(CSIDPHY_CLK_PHASE_MASK, priv->clk_phase); > + writel(val, priv->phy_base + CSIDPHY_LANE_CLK_3_PHASE); > + } > + > write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1); > write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN, > GENMASK(priv->config.lanes - 1, 0)); > @@ -449,6 +461,7 @@ static int rockchip_inno_csidphy_probe(struct platform_device *pdev) > struct device *dev = &pdev->dev; > struct phy_provider *phy_provider; > struct phy *phy; > + u32 phase; > int ret; > > priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > @@ -464,6 +477,18 @@ static int rockchip_inno_csidphy_probe(struct platform_device *pdev) > return -ENODEV; > } > > + priv->clk_phase = -1; > + if (device_property_read_u32(dev, "rockchip,clk-lane-phase", > + &phase) == 0) { > + if (phase > 7) { > + dev_warn(dev, > + "invalid rockchip,clk-lane-phase %u, using default %u\n", > + phase, CSIDPHY_CLK_PHASE_DEFAULT); > + phase = CSIDPHY_CLK_PHASE_DEFAULT; > + } > + priv->clk_phase = phase; > + } > + > priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, > "rockchip,grf"); > if (IS_ERR(priv->grf)) { > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip