From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: Re: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions Date: Thu, 16 Jan 2020 16:59:20 +0530 Message-ID: References: <20191231113534.30405-1-kishon@ti.com> <20191231113534.30405-3-kishon@ti.com> <20200115014026.GA10726@bogus> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20200115014026.GA10726@bogus> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane-mx.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Rob Herring Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Lorenzo Pieralisi , Heiko Stuebner , Arnd Bergmann , Jonathan Corbet , Jingoo Han , Shawn Lin , linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Tom Joseph , Greg Kroah-Hartman , Gustavo Pimentel , Bjorn Helgaas , Andrew Murray , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-rockchip.vger.kernel.org Hi Rob, On 15/01/20 7:10 AM, Rob Herring wrote: > On Tue, Dec 31, 2019 at 05:05:29PM +0530, Kishon Vijay Abraham I wrote: >> Add binding to specify maximum number of virtual functions that can be >> associated with each physical function. >> >> Signed-off-by: Kishon Vijay Abraham I >> --- >> .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 2 ++ >> .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 8 ++++++++ >> 2 files changed, 10 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >> index 4a0475e2ba7e..432578202733 100644 >> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >> @@ -9,6 +9,8 @@ Required properties: >> >> Optional properties: >> - max-functions: Maximum number of functions that can be configured (default 1). >> +- max-virtual-functions: Maximum number of virtual functions that can be >> + associated with each physical function. >> - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more >> than one in the list. If only one PHY listed it must manage all lanes. >> - phy-names: List of names to identify the PHY. >> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml >> index 4621c62016c7..1d4964ba494f 100644 >> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml >> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml >> @@ -61,6 +61,12 @@ properties: >> minimum: 1 >> maximum: 6 >> >> + max-virtual-functions: >> + minItems: 1 >> + maxItems: 6 > > Is there a PCIe spec limit to number of virtual functions per phy > function? Or 2^32 virtual functions is okay. The PCIe spec provides a 16 bit field to specify number of virtual functions in the SR-IOV extended capability. > >> + description: As defined in >> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > > I suspect this this be a common property. Right now we don't have common EP property binding across all controllers. Maybe should create one? Thanks Kishon