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[2a02:3100:a8e9:c501:f941:243b:87f6:e5a2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fcd1149e0sm198706585e9.13.2026.09.20.23.00.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 20 Sep 2026 23:00:25 -0700 (PDT) From: Karl Mehltretter To: Russell King , Dmitry Baryshkov , Sudeep Holla Cc: Karl Mehltretter , Pierre Gondois , Linus Walleij , Radu Rendec , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-arm-kernel@lists.infradead.org, linux-rt-devel@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 2/4] ARM: cacheinfo: count external caches in early_cache_level() Date: Mon, 21 Sep 2026 08:00:11 +0200 Message-Id: <20260921-arm-cacheinfo-v2-5892c4531ad9-2@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20260921-arm-cacheinfo-v2-5892c4531ad9-0@gmail.com> References: <20260912195552.76673-1-kmehltretter@gmail.com> <20260921-arm-cacheinfo-v2-5892c4531ad9-0@gmail.com> Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: linux-rt-devel@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit early_cache_level() counts only caches described by CLIDR. An external PL310 is absent from CLIDR, and its arm,pl310-cache compatible is not accepted by init_of_cache_level(), so early allocation falls back to an incomplete count. init_cache_level() later adds the DT-described L2, forcing reallocation on the secondary CPU with interrupts disabled. This defeats early allocation on PREEMPT_RT. Use init_cache_level() for early sizing too, so the initial allocation includes external caches described by the device tree. Cc: stable@vger.kernel.org Tested-by: Sebastian Andrzej Siewior Link: https://lore.kernel.org/r/20260912195552.76673-3-kmehltretter@gmail.com/ Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Fresh full-series rc1 retest: three builds and seven QEMU boot/CPU hotplug checks passed; see the v2 cover for the matrix. The detailed testing below was performed for v1, before this rebase. Without this patch, patch 4 keeps the warning on QEMU vexpress-a9 (4 Cortex-A9, PL310): the early size is 2 leaves, init_cache_level() wants 3, and init_level_allocate_ci() reallocates on the secondary CPU. With it the warning is gone and the cache sysfs tree is unchanged (L1 data, L1 instruction, L2 unified shared by all CPUs). arch/arm/kernel/cacheinfo.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c index 860eeb03cfe5..31591c947254 100644 --- a/arch/arm/kernel/cacheinfo.c +++ b/arch/arm/kernel/cacheinfo.c @@ -111,13 +111,6 @@ static int detect_cache_level(unsigned int *level_p, unsigned int *leaves_p) return 0; } -int early_cache_level(unsigned int cpu) -{ - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - - return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); -} - int init_cache_level(unsigned int cpu) { unsigned int level, leaves; @@ -146,6 +139,11 @@ int init_cache_level(unsigned int cpu) return 0; } +int early_cache_level(unsigned int cpu) +{ + return init_cache_level(cpu); +} + int populate_cache_leaves(unsigned int cpu) { unsigned int level, idx;