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[2a02:3100:a8e9:c501:f941:243b:87f6:e5a2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fcd1149e0sm198706585e9.13.2026.09.20.23.00.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 20 Sep 2026 23:00:28 -0700 (PDT) From: Karl Mehltretter To: Russell King , Dmitry Baryshkov , Sudeep Holla Cc: Karl Mehltretter , Pierre Gondois , Linus Walleij , Radu Rendec , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-arm-kernel@lists.infradead.org, linux-rt-devel@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 4/4] ARM: topology: allocate the cacheinfo early on the boot CPU Date: Mon, 21 Sep 2026 08:00:13 +0200 Message-Id: <20260921-arm-cacheinfo-v2-5892c4531ad9-4@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20260921-arm-cacheinfo-v2-5892c4531ad9-0@gmail.com> References: <20260912195552.76673-1-kmehltretter@gmail.com> <20260921-arm-cacheinfo-v2-5892c4531ad9-0@gmail.com> Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: linux-rt-devel@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ARM secondary CPUs allocate cacheinfo in detect_cache_attributes(), called from secondary_start_kernel() with interrupts disabled. With PREEMPT_RT, the allocation takes a sleeping lock and triggers "BUG: sleeping function called from invalid context". Call fetch_cache_info() for each possible CPU from init_cpu_topology() on the boot CPU, following commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). This supplies the arrays before secondary CPUs populate them. Suppress -ENOENT and -EOPNOTSUPP, which leave cache detection to the existing late path. The CLIDR fallback uses the boot CPU's cache geometry. A secondary CPU with more cache leaves can still require late reallocation and trigger the warning. Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support") Cc: stable@vger.kernel.org Tested-by: Sebastian Andrzej Siewior Link: https://lore.kernel.org/r/20260912195552.76673-5-kmehltretter@gmail.com/ Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Fresh full-series rc1 retest: three builds and seven QEMU boot/CPU hotplug checks passed; see the v2 cover for the matrix. The detailed testing below was performed for v1, before this rebase. Full warning on QEMU virt, cortex-a15, 7.3-rc2, PREEMPT_RT: BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:48 in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1 Call trace: rt_spin_lock from ___slab_alloc+0x68/0x728 ... __kmalloc_noprof from detect_cache_attributes+0xe4/0x734 detect_cache_attributes from update_siblings_masks+0x10/0x174 update_siblings_masks from secondary_start_kernel+0xec/0x120 PREEMPT_RT became selectable on ARM in 7.1 with commit c6e61c06d606 ("ARM: 9463/1: Allow to enable RT"). The PREEMPT_RT patch queues carry that change for 6.18 and later, so 6.18.y is affected as well. QEMU virt, cortex-a15, PREEMPT_RT, 2 and 4 CPUs: the warning is gone, the cacheinfo sysfs tree is identical before and after, CPU 1 survives an offline/online cycle. Same on a non-RT build. QEMU realview-eb-mpcore, ARM11 MPCore, 4 CPUs, ARMv6 plus ARMv7 SMP kernel with PREEMPT_RT: fetch_cache_info() returns -EOPNOTSUPP through the CTR format check, no message, no cacheinfo before or after, CPU hotplug works, kernel messages otherwise identical. Raspberry Pi 400, four Cortex-A72 CPUs, 32-bit PREEMPT_RT 7.2.6-rc1, full series: the boot warning is absent and all 12 cache sysfs entries match the unpatched baseline and earlier topology-only run. The live DT describes the shared L2, exercising DT-based early allocation. CPU hotplug is unavailable on this platform. arch/arm/kernel/topology.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 2336ee2aa44a..e6b50cd43ce5 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include @@ -238,8 +239,20 @@ void store_cpu_topology(unsigned int cpuid) */ void __init init_cpu_topology(void) { + int cpu, ret; + reset_cpu_topology(); smp_wmb(); parse_dt_topology(); + + for_each_possible_cpu(cpu) { + ret = fetch_cache_info(cpu); + if (!ret) + continue; + /* CPUs without a usable CLIDR return -EOPNOTSUPP. */ + if (ret != -ENOENT && ret != -EOPNOTSUPP) + pr_err("Early cacheinfo failed, ret = %d\n", ret); + return; + } }