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[2a02:3100:aeb3:cd01:f139:812c:65df:b930]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bf63567esm62999745e9.10.2026.10.14.23.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 23:32:14 -0700 (PDT) Date: Thu, 15 Oct 2026 08:32:12 +0200 From: Karl Mehltretter To: Steven Rostedt Cc: Peter Zijlstra , Thomas Gleixner , Sebastian Andrzej Siewior , Frederic Weisbecker , Clark Williams , Boqun Feng , Lyude Paul , Joel Fernandes , Alexander Potapenko , Marco Elver , Jonathan Corbet , Bradley Morgan , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev, Shuah Khan , Randy Dunlap , "Mukesh Kumar Chaurasiya (IBM)" Subject: Re: [PATCH v6] softirq: Preserve interrupt context during IRQ exit Message-ID: References: <20261011060742.30584-1-kmehltretter@gmail.com> <20261014120524.5e6e6efe@gandalf.local.home> Precedence: bulk X-Mailing-List: linux-rt-devel@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261014120524.5e6e6efe@gandalf.local.home> On Wed, Oct 14, 2026 at 12:05:24PM +0100, Steven Rostedt wrote: > LGTM. > > So this handles the transition between hard irq and softirq? > > I wish there was a way to get preempt count updated earlier on entering a > hard irq so I can get rid of the transition bit in the trace recursion. As > there's still places that can trigger a trace in the hard irq before > preempt count is updated. > Yes, this handles the hardirq-to-softirq transition on IRQ exit. I am looking into whether the preempt count can be updated before any traceable code can run, as a potential follow-up RFC. If that works, it may allow the transition bit to be removed from trace recursion. Thanks, Karl