* x86 question ...
@ 2012-09-10 22:55 Lars Segerlund
2012-09-11 11:42 ` Gilles Chanteperdrix
0 siblings, 1 reply; 2+ messages in thread
From: Lars Segerlund @ 2012-09-10 22:55 UTC (permalink / raw)
To: linux-rt-users
I read that on arm there was a set of patches for using a single
virtual adress space, ( ie. all processes live in the same mapping so
to speak , but still protected ), which greatly reduced context
switching time on that platform, does anyone know if the same would be
true for x86 ( maily x86_64 ).
I believe the main gain was in not needing to invalidate the caches
or something like that, it came to mind after seeing a paper on
uClinux with rt versus regular linux and the latency times ?
I have been googling a bit but I not up to date on cache & memory
architecture on both platforms.
It's easy to se that uClinux would have an advantage :-D ... no TLB
and such, only directly mapped memory. But would a single adress space
for all processes have the same effect ?
Just curious ....
/ regards, Lars Segerlund.
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: x86 question ...
2012-09-10 22:55 x86 question Lars Segerlund
@ 2012-09-11 11:42 ` Gilles Chanteperdrix
0 siblings, 0 replies; 2+ messages in thread
From: Gilles Chanteperdrix @ 2012-09-11 11:42 UTC (permalink / raw)
To: Lars Segerlund; +Cc: linux-rt-users
On 09/11/2012 12:55 AM, Lars Segerlund wrote:
> I read that on arm there was a set of patches for using a single
> virtual adress space, ( ie. all processes live in the same mapping so
> to speak , but still protected ), which greatly reduced context
> switching time on that platform, does anyone know if the same would be
> true for x86 ( maily x86_64 ).
If the patch you are talking about is the FCSE patch, no, it will not
work for x86:
- the FCSE patch allows avoiding to flush the cache at every context
switch on armv4 and armv5, because their cache architecture (VIVT)
requires this cache flush otherwise, but x86 have a PIPT cache, so, no
cache flush is needed during the context switches;
- the FCSE patch requires hardware support, the FCSE (Fast Context
Switch Extension) pid register, despite the fact that every process
lives in a separate 32MiB slice below the 3GB limit, its address-space
appears to be [0;32MiB[, this allows "fork" to work; x86, as far as I
know, has no such hardware.
The advantage compared to uCLinux is that you still have memory
protection, but the performances are probably a bit worse because the
TLB is still invalidated at every context switch. So, these are
different trade-off.
--
Gilles.
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2012-09-10 22:55 x86 question Lars Segerlund
2012-09-11 11:42 ` Gilles Chanteperdrix
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