From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
To: Thomas Gleixner <tglx@linutronix.de>,
Grygorii Strashko <grygorii.strashko@ti.com>
Cc: linux-rt-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Sekhar Nori <nsekhar@ti.com>
Subject: Re: [v4.1.10-rt10][PATCH 1/2] genirq: introduce new generic_handle_irq_rt_wa() api
Date: Tue, 3 Nov 2015 21:18:28 +0100 [thread overview]
Message-ID: <56391694.3030105@linutronix.de> (raw)
In-Reply-To: <alpine.DEB.2.11.1511032014580.4032@nanos>
On 11/03/2015 08:51 PM, Thomas Gleixner wrote:
>> where MAX_MSI_IRQS = 32 now, but potentially can be increased up to 256.
>
> And you really oversimplified the code above. The reality is:
>
> for (i = 0; i < MAX_MSI_CTRLS: i++) {
> u32 status = read_msi_ctrl(i);
>
> for_each_bit(status)
> handle_irq();
> }
>
> So sure, the worst case here is MAX_MSI_CTRLS * 32, but if all
> possible 256 MSI interrupts are pending at the same time, you have
> other problems than that.
With threaded interrupts we would have 256 invocations of
wake_up_process() so nothing should take ages.
> Thanks,
>
> tglx
Sebastian
next prev parent reply other threads:[~2015-11-03 20:18 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-02 19:30 [v4.1.10-rt10][PATCH 0/2] PCI: dra7xx/dwc: fix "WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 handle_irq_event_percpu" Grygorii Strashko
2015-11-02 19:30 ` [v4.1.10-rt10][PATCH 1/2] genirq: introduce new generic_handle_irq_rt_wa() api Grygorii Strashko
2015-11-02 19:38 ` Thomas Gleixner
2015-11-03 19:11 ` Grygorii Strashko
2015-11-03 19:51 ` Thomas Gleixner
2015-11-03 20:18 ` Sebastian Andrzej Siewior [this message]
2015-11-05 16:44 ` Grygorii Strashko
2015-11-02 19:30 ` [v4.1.10-rt10] [PATCH 2/2] PCI: dra7xx: fix "WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 handle_irq_event_percpu" Grygorii Strashko
2015-11-03 13:46 ` [v4.1.10-rt10][PATCH 0/2] PCI: dra7xx/dwc: " Sebastian Andrzej Siewior
2015-11-03 19:11 ` Grygorii Strashko
2015-11-03 20:01 ` Thomas Gleixner
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