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From: Punit Agrawal <punitagrawal@gmail.com>
To: nsaenzju@redhat.com
Cc: jkacur@redhat.com, Peter Xu <peterx@redhat.com>,
	linux-rt-users@vger.kernel.org, williams@redhat.com
Subject: Re: [PATCH v2 2/3] oslat: Add aarch64 support
Date: Wed, 15 Sep 2021 10:52:03 +0900	[thread overview]
Message-ID: <874kam8v24.fsf@stealth> (raw)
In-Reply-To: <fe15dafd9a6b6ee0d7f8a9f53e9acb6f4288046f.camel@redhat.com> (nsaenzju@redhat.com's message of "Tue, 14 Sep 2021 12:16:05 +0200")

nsaenzju@redhat.com writes:

> On Tue, 2021-09-14 at 10:52 +0900, Punit Agrawal wrote:
>> Hi Nicolas,
>> 
>> Apologies for the late comment. I just caught up with the thread.
>
> No worries, thanks for the input!
>
> [...]
>
>> > +static inline void frc(uint64_t *pval)
>> > +{
>> > +	/*
>> > +	 * This isb() is required to prevent that the counter value
>> > +	 * is speculated.
>> > +	 */
>> > +	__asm__ __volatile__("isb" : : : "memory");
>> > +	__asm__ __volatile__("mrs %0, cntvct_el0" : "=r" (*pval) :: "memory");
>> > +
>> 
>> Although the isb() ensures completion of instructions before the counter
>> is read, I think there is still the problem of speculative execution of
>> instructions after the counter read being moved forward. See the
>> examples in Arm ARM DDI 0487F.b Section D11.2.2 "The Virtual counter"
>> 
>> So from my understanding the problem would be something like below -
>> 
>> isb()
>> ...  <-  speculatively executed instructions from after the counter read
>> mrs %0, cntvct_el0
>> 
>> This would skew the counter value to a later point than what is intended
>> - a following isb() would address the issue.
>
> For the record, here's what the Arm ARM states:
>
>   Accesses to memory appearing in program order after the read of the counter
>   are executed before the counter has been read. [...]
>
>   To ensure that a memory access only occurs after a read of the counter, the
>   following sequence should be used:
>
>     MRS Xn, CNTVCT_EL0
>     ISB
>     LDR Xa, [Xb] ; this load will be executed after the timer has been read"
>
> As stated in the commit description, I made sure the program logic can't suffer
> from this. I hadn't thought of the timing angle though. I doubt we'll see any
> difference, given we have a 1us granularity, but I don't mind adding it for the
> sake of correctness.

Thanks - indeed that's the part I was referring to. Indeed the impact
will likely be low or none here but thought I'd mention the issue since
I noticed it while going through the patch.

Punit

[...]


  parent reply	other threads:[~2021-09-15  1:52 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13  8:39 [PATCH v2 1/3] oslat: Rename cpu_mhz/cpu_hz to counter_mhz/counter_hz Nicolas Saenz Julienne
2021-09-13  8:39 ` [PATCH v2 2/3] oslat: Add aarch64 support Nicolas Saenz Julienne
2021-09-13 18:38   ` John Kacur
2021-09-14  1:52   ` Punit Agrawal
2021-09-14 10:16     ` nsaenzju
2021-09-14 12:48       ` John Kacur
2021-09-15  1:52       ` Punit Agrawal [this message]
2021-09-13  8:39 ` [PATCH v2 3/3] oslat: Allow for arch specific counter frequency measurements Nicolas Saenz Julienne
2021-09-13 18:39   ` John Kacur
2021-09-13 13:35 ` [PATCH v2 1/3] oslat: Rename cpu_mhz/cpu_hz to counter_mhz/counter_hz John Kacur
2021-09-13 14:57   ` Peter Xu
2021-09-13 18:39     ` John Kacur
2021-09-13 18:38 ` John Kacur

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