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[122.211.248.161]) by smtp.gmail.com with ESMTPSA id 19sm11861423pfh.12.2021.09.14.18.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 18:52:06 -0700 (PDT) From: Punit Agrawal To: nsaenzju@redhat.com Cc: jkacur@redhat.com, Peter Xu , linux-rt-users@vger.kernel.org, williams@redhat.com Subject: Re: [PATCH v2 2/3] oslat: Add aarch64 support References: <20210913083908.48408-1-nsaenzju@redhat.com> <20210913083908.48408-2-nsaenzju@redhat.com> <87ee9r9b5e.fsf@stealth> Date: Wed, 15 Sep 2021 10:52:03 +0900 In-Reply-To: (nsaenzju@redhat.com's message of "Tue, 14 Sep 2021 12:16:05 +0200") Message-ID: <874kam8v24.fsf@stealth> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-rt-users@vger.kernel.org nsaenzju@redhat.com writes: > On Tue, 2021-09-14 at 10:52 +0900, Punit Agrawal wrote: >> Hi Nicolas, >> >> Apologies for the late comment. I just caught up with the thread. > > No worries, thanks for the input! > > [...] > >> > +static inline void frc(uint64_t *pval) >> > +{ >> > + /* >> > + * This isb() is required to prevent that the counter value >> > + * is speculated. >> > + */ >> > + __asm__ __volatile__("isb" : : : "memory"); >> > + __asm__ __volatile__("mrs %0, cntvct_el0" : "=r" (*pval) :: "memory"); >> > + >> >> Although the isb() ensures completion of instructions before the counter >> is read, I think there is still the problem of speculative execution of >> instructions after the counter read being moved forward. See the >> examples in Arm ARM DDI 0487F.b Section D11.2.2 "The Virtual counter" >> >> So from my understanding the problem would be something like below - >> >> isb() >> ... <- speculatively executed instructions from after the counter read >> mrs %0, cntvct_el0 >> >> This would skew the counter value to a later point than what is intended >> - a following isb() would address the issue. > > For the record, here's what the Arm ARM states: > > Accesses to memory appearing in program order after the read of the counter > are executed before the counter has been read. [...] > > To ensure that a memory access only occurs after a read of the counter, the > following sequence should be used: > > MRS Xn, CNTVCT_EL0 > ISB > LDR Xa, [Xb] ; this load will be executed after the timer has been read" > > As stated in the commit description, I made sure the program logic can't suffer > from this. I hadn't thought of the timing angle though. I doubt we'll see any > difference, given we have a 1us granularity, but I don't mind adding it for the > sake of correctness. Thanks - indeed that's the part I was referring to. Indeed the impact will likely be low or none here but thought I'd mention the issue since I noticed it while going through the patch. Punit [...]