From mboxrd@z Thu Jan  1 00:00:00 1970
From: Christoph Mathys <eraserix@gmail.com>
Subject: Re: [PATCH v2] drm/i915: Do not flush caches on RT, print a warning instead
Date: Mon, 10 Jun 2013 08:30:35 +0200
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Cc: Steven Rostedt <rostedt@goodmis.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Daniel Vetter <daniel@ffwll.ch>,
	Linux RT Users <linux-rt-users@vger.kernel.org>
To: Carsten Emde <C.Emde@osadl.org>
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On Sun, Jun 9, 2013 at 1:45 PM, Carsten Emde <C.Emde@osadl.org> wrote:
> Invalidating and flushing all caches may introduce long latencies of up
> to several milliseconds. Do not execute it in PREEMPT_RT_FULL kernels,
> warn once instead and propose to pin all GPU renderering tasks to a
> single CPU, if possible.
>
> Original commit:
> 25ff1195f8a0b3724541ae7bbe331b4296de9c06 upstream.
>
> Original log:
> In order to fully serialize access to the fenced region and the update
> to the fence register we need to take extreme measures on SNB+, and
> manually flush writes to memory prior to writing the fence register in
> conjunction with the memory barriers placed around the register write.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>

This fixes the problem for me on 3.6.11.5-rt37. Thanks, Carsten!

Christoph