From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-f49.google.com (mail-wg0-f49.google.com. [74.125.82.49]) by gmr-mx.google.com with ESMTPS id k2si392395wif.0.2015.05.11.03.53.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 May 2015 03:53:52 -0700 (PDT) Received: by mail-wg0-f49.google.com with SMTP id u9so124204747wgi.3 for ; Mon, 11 May 2015 03:53:52 -0700 (PDT) Date: Mon, 11 May 2015 11:53:47 +0100 From: Lee Jones To: Daniel Lezcano Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@stlinux.com, devicetree@vger.kernel.org, tglx@linutronix.de, wim@iguana.be, a.zummo@towertech.it, linux-watchdog@vger.kernel.org, rtc-linux@googlegroups.com, linux@roeck-us.net Subject: [rtc-linux] Re: [PATCH 02/12] clocksource: sti: Provide support for the ST LPC Clocksource IP Message-ID: <20150511105347.GA20742@x1> References: <1431005924-21777-1-git-send-email-lee.jones@linaro.org> <1431005924-21777-3-git-send-email-lee.jones@linaro.org> <55506B87.3070807@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 In-Reply-To: <55506B87.3070807@linaro.org> Reply-To: rtc-linux@googlegroups.com List-ID: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , On Mon, 11 May 2015, Daniel Lezcano wrote: > On 05/07/2015 03:38 PM, Lee Jones wrote: > >This IP is shared with Watchdog and RTC functionality. Only one of > >these IPs can be used at the same time. We use the device-driver > >model combined with a DT 'mode' property to enforce this. > > > >The ST LPC Clocksource IP can be used as the system (tick) timer. > > > >Signed-off-by: Lee Jones > >--- > > drivers/clocksource/Kconfig | 8 +++ > > drivers/clocksource/Makefile | 1 + > > drivers/clocksource/clksrc_st_lpc.c | 123 ++++++++++++++++++++++++++++= ++++++++ > > 3 files changed, 132 insertions(+) > > create mode 100644 drivers/clocksource/clksrc_st_lpc.c > > > >diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > >index 68161f7..ac424cf 100644 > >--- a/drivers/clocksource/Kconfig > >+++ b/drivers/clocksource/Kconfig > >@@ -250,4 +250,12 @@ config CLKSRC_PXA > > help > > This enables OST0 support available on PXA and SA-11x0 > > platforms. > >+ > >+config CLKSRC_ST_LPC > >+ bool > >+ depends on ARCH_STI > >+ select CLKSRC_OF if OF > >+ help > >+ Enable this option to use the Low Power controller timer > >+ as clocksource. > > endmenu > >diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile > >index 752d5c7..e08da4d 100644 > >--- a/drivers/clocksource/Makefile > >+++ b/drivers/clocksource/Makefile > >@@ -51,3 +51,4 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP) +=3D timer-integrator= -ap.o > > obj-$(CONFIG_CLKSRC_VERSATILE) +=3D versatile.o > > obj-$(CONFIG_CLKSRC_MIPS_GIC) +=3D mips-gic-timer.o > > obj-$(CONFIG_ASM9260_TIMER) +=3D asm9260_timer.o > >+obj-$(CONFIG_CLKSRC_ST_LPC) +=3D clksrc_st_lpc.o > >diff --git a/drivers/clocksource/clksrc_st_lpc.c b/drivers/clocksource/c= lksrc_st_lpc.c > >new file mode 100644 > >index 0000000..18a7dcd0 > >--- /dev/null > >+++ b/drivers/clocksource/clksrc_st_lpc.c > >@@ -0,0 +1,123 @@ > >+/* > >+ * Clocksource using the Low Power Timer found in the Low Power Control= ler (LPC) > >+ * > >+ * Copyright (C) 2015 STMicroelectronics =E2=80=93 All Rights Reserved > >+ * > >+ * Author(s): Francesco Virlinzi > >+ * Ajit Pal Singh > >+ * > >+ * This program is free software; you can redistribute it and/or modify > >+ * it under the terms of the GNU General Public License as published by > >+ * the Free Software Foundation; either version 2 of the License, or > >+ * (at your option) any later version. > >+ */ > >+ > >+#include > >+#include > >+#include > >+#include > >+#include > >+ > >+#include > >+ > >+/* Low Power Timer */ > >+#define LPC_LPT_LSB_OFF 0x400 > >+#define LPC_LPT_MSB_OFF 0x404 > >+#define LPC_LPT_START_OFF 0x408 > >+ > >+static struct st_clksrc_ddata { > >+ struct clk *clk; > >+ void __iomem *base; > >+} ddata; > >+ > >+static void st_clksrc_reset(void) > >+{ > >+ writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); > >+ writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); > >+ writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); > >+ writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); > >+} > >+ > >+static int __init st_clksrc_init(void) > >+{ > >+ unsigned long rate; > >+ int ret; > >+ > >+ st_clksrc_reset(); > >+ > >+ rate =3D clk_get_rate(ddata.clk); > >+ > >+ ret =3D clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, > >+ "clksrc-st-lpc", rate, 300, 32, > >+ clocksource_mmio_readl_up); > >+ if (ret) { > >+ pr_err("clksrc-st-lpc: Failed to register clocksource\n"); > >+ return ret; > >+ } > >+ > >+ return 0; > >+} > >+ > >+static int st_clksrc_setup_clk(struct device_node *np) > >+{ > >+ struct clk *clk; > >+ int ret; > >+ > >+ clk =3D of_clk_get(np, 0); > >+ if (IS_ERR(clk)) { > >+ pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); > >+ ret =3D PTR_ERR(clk); > >+ return ret; >=20 > return PTR_ERR(clk); >=20 > so you can get rid of the 'int ret' variable. Absolutely. Good spot. > >+ } > >+ > >+ if (clk_prepare_enable(clk)) { > >+ pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); > >+ return -EINVAL; > >+ } > >+ > >+ if (!clk_get_rate(clk)) { > >+ pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); > >+ clk_disable_unprepare(clk); > >+ return -EINVAL; > >+ } > >+ > >+ ddata.clk =3D clk; > >+ > >+ return 0; > >+} > >+ > >+static void __init st_clksrc_of_register(struct device_node *np) > >+{ > >+ int ret; > >+ uint32_t mode; > >+ > >+ ret =3D of_property_read_u32(np, "st,lpc-mode", &mode); > >+ if (ret) { > >+ pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); > >+ return; > >+ } > >+ > >+ /* LPC can either run as a Clocksource or in RTC or WDT mode */ > >+ if (mode !=3D ST_LPC_MODE_CLKSRC) > >+ return; >=20 > I am confused with this patch description + comment and the patch > 1's description. >=20 > For the former, I understand the LPC could be in RTC or WDT mode and > used as a clocksource (clksrc + rtc / clksrc + wdt), for the latter > I understand there are three modes clocksource, rtc and watchdog > (mutually exclusive). Could you clarify ? They are all mutually exclusive. I will fix-up the commit log to re-enforce this. > >+ > >+ ddata.base =3D of_iomap(np, 0); > >+ if (!ddata.base) { > >+ pr_err("clksrc-st-lpc: Unable to map iomem\n"); > >+ return; > >+ } > >+ > >+ if (st_clksrc_setup_clk(np)) { > >+ iounmap(ddata.base); > >+ return; > >+ } > >+ > >+ if (st_clksrc_init()) { > >+ iounmap(ddata.base); > >+ return; > >+ } > >+ > >+ pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", > >+ clk_get_rate(ddata.clk)); > >+} > >+CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register); > > >=20 >=20 --=20 Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org =E2=94=82 Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog --=20 --=20 You received this message because you are subscribed to "rtc-linux". Membership options at http://groups.google.com/group/rtc-linux . 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