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[46.91.239.54]) by smtp.gmail.com with ESMTPSA id z5sm2735022wrh.16.2019.06.14.06.22.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 14 Jun 2019 06:22:54 -0700 (PDT) Date: Fri, 14 Jun 2019 15:22:53 +0200 From: Thierry Reding To: Dmitry Osipenko Cc: Daniel Lezcano , Thomas Gleixner , Alessandro Zummo , Alexandre Belloni , Jonathan Hunter , linux-tegra@vger.kernel.org, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] clocksource: tegra: Use rating when registering clock source Message-ID: <20190614132253.GE15526@ulmo> References: <20190614104747.19712-1-thierry.reding@gmail.com> <8ff5d2da-907e-611c-ec82-bbe50197c2f4@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="idY8LE8SD6/8DnRI" Content-Disposition: inline In-Reply-To: <8ff5d2da-907e-611c-ec82-bbe50197c2f4@gmail.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org --idY8LE8SD6/8DnRI Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jun 14, 2019 at 03:24:07PM +0300, Dmitry Osipenko wrote: > 14.06.2019 13:47, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Thierry Reding > >=20 > > The rating is parameterized depending on SoC generation to make sure it > > takes precedence on implementations where the architected timer can't be > > used. This rating is already used for the clock event device. Use the > > same rating for the clock source to be consistent. > >=20 > > Signed-off-by: Thierry Reding > > --- > > drivers/clocksource/timer-tegra.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > >=20 > > diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/ti= mer-tegra.c > > index f6a8eb0d7322..e6608141cccb 100644 > > --- a/drivers/clocksource/timer-tegra.c > > +++ b/drivers/clocksource/timer-tegra.c > > @@ -318,7 +318,7 @@ static int __init tegra_init_timer(struct device_no= de *np, bool tegra20, > > sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz); > > =20 > > ret =3D clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, > > - "timer_us", TIMER_1MHz, 300, 32, > > + "timer_us", TIMER_1MHz, rating, 32, > > clocksource_mmio_readl_up); > > if (ret) > > pr_err("failed to register clocksource: %d\n", ret); > >=20 >=20 > Looks good. Although, could you please clarify whether arch-timer stops o= n T210 when CPU > enters deepest (powerdown) idle state? I'm starting to lose track a bit a= lready. Because > if arch-timer stops in the deepest idle state, then it's a bit odd that J= oseph didn't add > the clocksource for T210 in the first place and v5.1 probably shouldn't w= ork well because > of that already. Yes, the architected timer doesn't work across an SC7 (which is what the deepest idle state is called on Tegra210) transition, hence why we can't use it as a suspend clocksource. I actually sent out a patch to do that, earlier. And yes, it's entirely possible that v5.1 doesn't work in this regard, but we're not noticing that because we don't have suspend/resume support for Tegra210 anyway. There are a couple of missing pieces that we need in order to make it work. This change in particular is only going to affect the CPU idle state (CC7). Since the architected timer doesn't survive that either, we need the Tegra timer to be preferred over the architected timer for normal operation. All of these issues go away on Tegra186 and later, where the architected timer is in an always-on partition and has a PLL that remains on during SC7 (and CC7). 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