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[46.91.239.54]) by smtp.gmail.com with ESMTPSA id z6sm3466351wrw.2.2019.06.14.07.14.01 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 14 Jun 2019 07:14:01 -0700 (PDT) Date: Fri, 14 Jun 2019 16:14:00 +0200 From: Thierry Reding To: Dmitry Osipenko Cc: Daniel Lezcano , Thomas Gleixner , Alessandro Zummo , Alexandre Belloni , Jonathan Hunter , linux-tegra@vger.kernel.org, linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] rtc: tegra: Implement suspend clock source Message-ID: <20190614141400.GI15526@ulmo> References: <20190614104747.19712-1-thierry.reding@gmail.com> <20190614104747.19712-2-thierry.reding@gmail.com> <5a00bccf-6542-51bd-9030-99a59f14f2f9@gmail.com> <20190614134110.GF15526@ulmo> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="STPqjqpCrtky8aYs" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org --STPqjqpCrtky8aYs Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jun 14, 2019 at 04:49:44PM +0300, Dmitry Osipenko wrote: > 14.06.2019 16:41, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Fri, Jun 14, 2019 at 03:01:13PM +0300, Dmitry Osipenko wrote: > >> 14.06.2019 13:47, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > >>> From: Thierry Reding > >>> > >>> The suspend clock source for Tegra210 and earlier is currently > >>> implemented in the Tegra timer driver. However, the suspend clock sou= rce > >>> code accesses registers that are part of the RTC hardware block, so b= oth > >>> can step on each others' toes. In practice this isn't an issue, but > >>> there is no reason why the RTC driver can't implement the clock sourc= e, > >>> so move the code over to the tegra-rtc driver. > >>> > >>> Signed-off-by: Thierry Reding > >>> --- > >>> drivers/clocksource/timer-tegra.c | 44 -----------------------------= -- > >>> drivers/rtc/rtc-tegra.c | 42 +++++++++++++++++++++++++++++ > >>> 2 files changed, 42 insertions(+), 44 deletions(-) > >>> > >>> diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/= timer-tegra.c > >>> index e6608141cccb..87eac618924d 100644 > >>> --- a/drivers/clocksource/timer-tegra.c > >>> +++ b/drivers/clocksource/timer-tegra.c > >>> @@ -21,10 +21,6 @@ > >>> =20 > >>> #include "timer-of.h" > >>> =20 > >>> -#define RTC_SECONDS 0x08 > >>> -#define RTC_SHADOW_SECONDS 0x0c > >>> -#define RTC_MILLISECONDS 0x10 > >>> - > >>> #define TIMERUS_CNTR_1US 0x10 > >>> #define TIMERUS_USEC_CFG 0x14 > >>> #define TIMERUS_CNTR_FREEZE 0x4c > >>> @@ -164,34 +160,6 @@ static struct delay_timer tegra_delay_timer =3D { > >>> }; > >>> #endif > >>> =20 > >>> -static struct timer_of suspend_rtc_to =3D { > >>> - .flags =3D TIMER_OF_BASE | TIMER_OF_CLOCK, > >>> -}; > >>> - > >>> -/* > >>> - * tegra_rtc_read - Reads the Tegra RTC registers > >>> - * Care must be taken that this function is not called while the > >>> - * tegra_rtc driver could be executing to avoid race conditions > >>> - * on the RTC shadow register > >>> - */ > >>> -static u64 tegra_rtc_read_ms(struct clocksource *cs) > >>> -{ > >>> - void __iomem *reg_base =3D timer_of_base(&suspend_rtc_to); > >>> - > >>> - u32 ms =3D readl_relaxed(reg_base + RTC_MILLISECONDS); > >>> - u32 s =3D readl_relaxed(reg_base + RTC_SHADOW_SECONDS); > >>> - > >>> - return (u64)s * MSEC_PER_SEC + ms; > >>> -} > >>> - > >>> -static struct clocksource suspend_rtc_clocksource =3D { > >>> - .name =3D "tegra_suspend_timer", > >>> - .rating =3D 200, > >>> - .read =3D tegra_rtc_read_ms, > >>> - .mask =3D CLOCKSOURCE_MASK(32), > >>> - .flags =3D CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTO= P, > >>> -}; > >>> - > >>> static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) > >>> { > >>> if (tegra20) { > >>> @@ -385,15 +353,3 @@ static int __init tegra20_init_timer(struct devi= ce_node *np) > >>> return tegra_init_timer(np, true, rating); > >>> } > >>> TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init= _timer); > >>> - > >>> -static int __init tegra20_init_rtc(struct device_node *np) > >>> -{ > >>> - int ret; > >>> - > >>> - ret =3D timer_of_init(np, &suspend_rtc_to); > >>> - if (ret) > >>> - return ret; > >>> - > >>> - return clocksource_register_hz(&suspend_rtc_clocksource, 1000); > >>> -} > >>> -TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc= ); > >>> diff --git a/drivers/rtc/rtc-tegra.c b/drivers/rtc/rtc-tegra.c > >>> index 8fa1b3febf69..6da54264a27a 100644 > >>> --- a/drivers/rtc/rtc-tegra.c > >>> +++ b/drivers/rtc/rtc-tegra.c > >>> @@ -6,6 +6,7 @@ > >>> */ > >>> =20 > >>> #include > >>> +#include > >>> #include > >>> #include > >>> #include > >>> @@ -52,8 +53,15 @@ struct tegra_rtc_info { > >>> struct clk *clk; > >>> int irq; /* alarm and periodic IRQ */ > >>> spinlock_t lock; > >>> + > >>> + struct clocksource clksrc; > >>> }; > >>> =20 > >>> +static struct tegra_rtc_info *to_tegra_rtc(struct clocksource *clksr= c) > >>> +{ > >>> + return container_of(clksrc, struct tegra_rtc_info, clksrc); > >>> +} > >>> + > >>> /* > >>> * RTC hardware is busy when it is updating its values over AHB once= every > >>> * eight 32 kHz clocks (~250 us). Outside of these updates the CPU i= s free to > >>> @@ -268,6 +276,17 @@ static const struct rtc_class_ops tegra_rtc_ops = =3D { > >>> .alarm_irq_enable =3D tegra_rtc_alarm_irq_enable, > >>> }; > >>> =20 > >>> +static u64 tegra_rtc_read_ms(struct clocksource *clksrc) > >>> +{ > >>> + struct tegra_rtc_info *info =3D to_tegra_rtc(clksrc); > >>> + u32 ms, s; > >>> + > >>> + ms =3D readl_relaxed(info->base + TEGRA_RTC_REG_MILLI_SECONDS); > >>> + s =3D readl_relaxed(info->base + TEGRA_RTC_REG_SHADOW_SECONDS); > >>> + > >>> + return (u64)s * MSEC_PER_SEC + ms; > >>> +} > >>> + > >>> static const struct of_device_id tegra_rtc_dt_match[] =3D { > >>> { .compatible =3D "nvidia,tegra20-rtc", }, > >>> {} > >>> @@ -339,6 +358,28 @@ static int tegra_rtc_probe(struct platform_devic= e *pdev) > >>> goto disable_clk; > >>> } > >>> =20 > >>> + /* > >>> + * The Tegra RTC is the only reliable clock source that persists > >>> + * across an SC7 transition (VDD_CPU and VDD_CORE off) on Tegra210 > >>> + * and earlier. Starting with Tegra186, the ARM v8 architected timer > >>> + * is in an always on power partition and its reference clock keeps > >>> + * running during SC7. Therefore, we technically don't need to have > >>> + * the RTC register as a clock source on Tegra186 and later, but it > >>> + * doesn't hurt either, so we just register it unconditionally here. > >>> + */ > >>> + info->clksrc.name =3D "tegra_rtc"; > >>> + info->clksrc.rating =3D 200; > >>> + info->clksrc.read =3D tegra_rtc_read_ms; > >>> + info->clksrc.mask =3D CLOCKSOURCE_MASK(32); > >> > >> Hm.. shouldn't this be CLOCKSOURCE_MASK(52)? Given that there are 32 b= its for seconds and > >> 10bits for milliseconds. > >=20 > > Did you mean to say CLOCKSOURCE_MASK(42)? Yeah, that's probably better > > here. >=20 > Yes, 42 :) I'm wondering if that could perhaps be a little problematic because we're not actually using all of the 10 bits for the milliseconds. So the maximum value that we can return is: 4294967296 * 1000 + 999 =3D 4294967296999 However, the maximum value for a 42 bit mask is: 2^42 - 1 =3D 4398046511103 That mask is only used in order to wrap around in delta computations. So I can imagine a situation where we'd end up with a wrong value in the delta. I suppose this can only really happen if the two samples are very far apart in time, so maybe this isn't worth worrying about. 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