From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Michael McCormick <michael.mccormick@enatel.net>
Cc: a.zummo@towertech.it, linux-rtc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] rtc: pcf85063: Add support for specifying the clkout frequency from device tree node.
Date: Fri, 19 Jul 2019 15:56:30 +0200 [thread overview]
Message-ID: <20190719135630.GD4012@piout.net> (raw)
In-Reply-To: <20190704022439.GA13102@michael-Latitude-5590>
Hello,
On 04/07/2019 14:24:39+1200, Michael McCormick wrote:
> Primarily this allows the clkout signal to be disabled and save some
> power when running off battery backup. However, all hardware implemented
> values are implemented. Uses default value of 32768Hz if node is not
> specified.
>
the proper way of doing that is to register the clkout signal in the
common clock framework. You can hava a look at rtc-pcf8563.c or rtc-m41t80.c
> Signed-off-by: Michael McCormick <michael.mccormick@enatel.net>
> ---
> drivers/rtc/rtc-pcf85063.c | 52 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/rtc/rtc-pcf85063.c b/drivers/rtc/rtc-pcf85063.c
> index 1afa6d9fa9fb..5c19381899ed 100644
> --- a/drivers/rtc/rtc-pcf85063.c
> +++ b/drivers/rtc/rtc-pcf85063.c
> @@ -37,6 +37,9 @@
> #define PCF85063_REG_CTRL2 0x01
> #define PCF85063_CTRL2_AF BIT(6)
> #define PCF85063_CTRL2_AIE BIT(7)
> +#define PCF85063_CTRL2_COF2 BIT(2)
> +#define PCF85063_CTRL2_COF1 BIT(1)
> +#define PCF85063_CTRL2_COF0 BIT(0)
>
> #define PCF85063_REG_OFFSET 0x02
> #define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
> @@ -369,6 +372,51 @@ static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
> PCF85063_REG_CTRL1_CAP_SEL, reg);
> }
>
> +static int pcf85063_set_clkout_mode(struct pcf85063 *pcf85063,
> + const struct device_node *np)
> +{
> + u32 load = 32768;
> + u8 reg = 0;
> +
> + of_property_read_u32(np, "clockout-frequency", &load);
> + switch (load) {
> + case 0:
> + reg = PCF85063_CTRL2_COF2 | PCF85063_CTRL2_COF1 |
> + PCF85063_CTRL2_COF0;
> + break;
> + case 1:
> + reg = PCF85063_CTRL2_COF2 | PCF85063_CTRL2_COF1;
> + break;
> + case 1024:
> + reg = PCF85063_CTRL2_COF2 | PCF85063_CTRL2_COF0;
> + break;
> + case 2048:
> + reg = PCF85063_CTRL2_COF2;
> + break;
> + case 4096:
> + reg = PCF85063_CTRL2_COF1 | PCF85063_CTRL2_COF0;
> + break;
> + case 8192:
> + reg = PCF85063_CTRL2_COF1;
> + break;
> + case 16384:
> + reg = PCF85063_CTRL2_COF0;
> + break;
> + case 32768:
> + reg = 0;
> + break;
> + default:
> + dev_warn(&pcf85063->rtc->dev,
> + "Unknown clockout-frequency: %d. Assuming 32768", load);
> + reg = 0;
> + break;
> + }
> +
> + return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
> + PCF85063_CTRL2_COF2 | PCF85063_CTRL2_COF1 |
> + PCF85063_CTRL2_COF0, reg);
> +}
> +
> static const struct pcf85063_config pcf85063a_config = {
> .regmap = {
> .reg_bits = 8,
> @@ -443,6 +491,10 @@ static int pcf85063_probe(struct i2c_client *client)
> dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
> err);
>
> + err = pcf85063_set_clkout_mode(pcf85063, client->dev.of_node);
> + if (err < 0)
> + dev_warn(&client->dev, "failed to set clock out mode: %d", err);
> +
> pcf85063->rtc->ops = &pcf85063_rtc_ops;
> pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
> pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
> --
> 2.17.1
>
>
>
> **CONFIDENTIALITY STATEMENT**
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--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
prev parent reply other threads:[~2019-07-19 13:56 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-04 2:24 [PATCH] rtc: pcf85063: Add support for specifying the clkout frequency from device tree node Michael McCormick
2019-07-19 13:56 ` Alexandre Belloni [this message]
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