* [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC
@ 2024-10-30 11:01 Claudiu
2024-10-30 11:01 ` [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Claudiu
` (11 more replies)
0 siblings, 12 replies; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi,
On the Renesas RZ/G3S SoC the RTC clock is provided by the VBATTB
IP. A 32 KHz crystall oscillator could be connected to the VBATTB
input pins. The logic to control this clock (and pass it to RTC)
is inside the VBATTB IP. For this, the clk-vbattb driver was added
(patches 01-03/12).
Patches:
- 01-03/10: add VBATTB support that provides the RTC clock
- 04-05/10: add the RTC driver
- 06-09/10: update the device trees with proper nodes to enable RTC
- 10/10: enable proper config flags for RTC to work on RZ/G3S SoC
Merge strategy, if any:
- clock patches (01-03/10) need to go though the same tree because of
patch 03/10 using the devm_clk_hw_register_gate_parent_hw() introduced
in patch 02/12
- RTC patches (04-05/10) can go though RTC tree
- DTS and defconfig patches can go though Renesas tree
Thank you,
Claudiu Beznea
Changes in v5:
- dropped patches already applied
- fixed build on rtc yaml file
- fixed indentation in patch 01/10 description
- collected tags
- per patch changes are listed in individual patches
Changes in v4:
- added patches
"dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC"
"clk: renesas: r9a08g045: Add power domain for RTC"
- squashed the following patches from v3:
"Add clock IDs for the VBATTB controller"
"dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB"
- fixed typos in commit description
- moved assigned-clocks, assigned-clock-parents from the RTC
documentation to the VBATTB documentation; same adjustment has been
done on the device tree patches
- renamed include/dt-bindings/clock/r9a08g045-vbattb.h to
include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
- used quartz-load-femtofarads
- used RTC_TIMESTAMP_BEGIN_2000 and RTC_TIMESTAMP_BEGIN_2099 in the RTC
driver and added a comment in remove API to mention RTC cannot power
on the system
- squashed defconfig patches
- collected tags
- per patch changes are listed in individual patches
Changes in v3:
- dropped patches "mfd: renesas-vbattb: Add a MFD driver for the Renesas
VBATTB IP"
- added patches:
-- dt-bindings: clock: r9a08g045-vbattb: Add clock IDs for
the VBATTB controller
-- clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw()
- moved Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml
to Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
- addressed review comments
- per patch changes are listed in individual patches
Changes in v2:
- dropped patch "clk: renesas: r9a08g045: Add clock, reset and power domain
support for the VBATTB IP" as it was already integrated
- kept only a documentation file for both VBATT MFD and clock drivers as
suggested
- addressed review comments
- used cleanup.h lock helpers
- update startup sequence for the RTC driver
- switch to 24 hours mode on the RTC driver
- fixed range for the RTC driver
- added a generic compatible for the RTC driver as this will also be
used by RZ/V2H
- used clkin/xin clock names for the VBATTB clock driver to determine
if bypass should be configured on registers instead of having
dedicated DT property
- added mfd driver for VBATTB
- updated Kconfig flag names to include vendor name
- removed DT node labels from Documentation files
- used items to describe the interrupts and clocks
Claudiu Beznea (10):
dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw()
clk: renesas: clk-vbattb: Add VBATTB clock driver
dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP
rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S
SoC
arm64: dts: renesas: r9a08g045: Add VBATTB node
arm64: dts: renesas: r9a08g045: Add RTC node
arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags
.../clock/renesas,r9a08g045-vbattb.yaml | 84 ++
.../bindings/rtc/renesas,rz-rtca3.yaml | 84 ++
MAINTAINERS | 8 +
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 34 +
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 16 +
arch/arm64/configs/defconfig | 2 +
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-vbattb.c | 205 ++++
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-renesas-rtca3.c | 899 ++++++++++++++++++
.../clock/renesas,r9a08g045-vbattb.h | 13 +
include/linux/clk-provider.h | 18 +
14 files changed, 1379 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
create mode 100644 drivers/clk/renesas/clk-vbattb.c
create mode 100644 drivers/rtc/rtc-renesas-rtca3.c
create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
--
2.39.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-31 7:46 ` Krzysztof Kozlowski
2024-10-30 11:01 ` [PATCH v5 02/10] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Claudiu
` (10 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
the tamper detector and a small general usage memory of 128B.
The VBATTB controller controls the clock for the RTC on the Renesas
RZ/G3S. The HW block diagram for the clock logic is as follows:
+----------+ XC `\
RTXIN --->| |----->| \ +----+ VBATTCLK
| 32K clock| | |----->|gate|----------->
| osc | XBYP | | +----+
RTXOUT --->| |----->| /
+----------+ ,/
One could connect as input to this HW block either a crystal or
an external clock device. This is board specific.
After discussions w/ Stephen Boyd the clock tree associated with this
hardware block was exported in Linux as:
input-xtal
xbyp
xc
mux
vbattclk
where:
- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
- xc, xbyp are mux inputs
- mux is the internal mux
- vbattclk is the gate clock that feeds in the end the RTC
to allow selecting the input of the MUX though assigned-clock DT
properties, using the already existing clock drivers and avoid adding
other DT properties.
This allows select the input of the mux based on the type of the
connected input clock:
- if the 32768 crystal is connected as input for the VBATTB,
the input of the mux should be xc
- if an external clock device is connected as input for the VBATTB the
input of the mux should be xbyp
Add bindings for the VBATTB controller.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- used spaces in the diagram from the patch description
- added "This is board specific" in the board description to emphasize
the usage of the assigned-clocks in the example
- added default for quartz-load-femtofarads
- collected tags
Changes in v4:
- squashed with patch "Add clock IDs for the VBATTB controller" from v3
- removed "oscillator" word from commit description
- added assigned-clocks, assigned-clock-parents to the documentation example
- used clock-controller for the node name
- used "quartz-load-femtofarads" property for the load capacitance
- renamed include/dt-bindings/clock/r9a08g045-vbattb.h to
include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
Changes in v3:
- moved the file to clock dt bindings directory as it is the
only functionality supported at the moment; the other functionalities
(tamper detector, SRAM) are offered though register spreaded
though the address space of the VBATTB IP and not actually
individual devices; the other functionalities are not
planned to be supported soon and if they will be I think they
fit better on auxiliary bus than MFD
- dropped interrupt names as requested in the review process
- dropped the inner node for clock controller
- added #clock-cells
- added rtx clock
- updated description for renesas,vbattb-load-nanofarads
- included dt-bindings/interrupt-controller/irq.h in examples section
Changes in v2:
- changed file name and compatible
- updated title, description sections
- added clock controller part documentation and drop dedicated file
for it included in v1
- used items to describe interrupts, interrupt-names, clocks, clock-names,
resets
- dropped node labels and status
- updated clock-names for clock controller to cope with the new
logic on detecting the necessity to setup bypass
.../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++
.../clock/renesas,r9a08g045-vbattb.h | 13 +++
2 files changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
new file mode 100644
index 000000000000..3707e4118949
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Battery Backup Function (VBATTB)
+
+description:
+ Renesas VBATTB is an always on powered module (backed by battery) which
+ controls the RTC clock (VBATTCLK), tamper detection logic and a small
+ general usage memory (128B).
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+properties:
+ compatible:
+ const: renesas,r9a08g045-vbattb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: tamper detector interrupt
+
+ clocks:
+ items:
+ - description: VBATTB module clock
+ - description: RTC input clock (crystal or external clock device)
+
+ clock-names:
+ items:
+ - const: bclk
+ - const: rtx
+
+ '#clock-cells':
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: VBATTB module reset
+
+ quartz-load-femtofarads:
+ description: load capacitance of the on board crystal
+ enum: [ 4000, 7000, 9000, 12500 ]
+ default: 4000
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a08g045-cpg.h>
+ #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ clock-controller@1005c000 {
+ compatible = "renesas,r9a08g045-vbattb";
+ reg = <0x1005c000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+ clock-names = "bclk", "rtx";
+ assigned-clocks = <&vbattb VBATTB_MUX>;
+ assigned-clock-parents = <&vbattb VBATTB_XC>;
+ #clock-cells = <1>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ quartz-load-femtofarads = <12500>;
+ };
diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
new file mode 100644
index 000000000000..67774eafad06
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
+#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
+
+#define VBATTB_XC 0
+#define VBATTB_XBYP 1
+#define VBATTB_MUX 2
+#define VBATTB_VBATTCLK 3
+
+#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 02/10] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw()
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
2024-10-30 11:01 ` [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 19:47 ` Stephen Boyd
2024-10-30 11:01 ` [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver Claudiu
` (9 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add devm_clk_hw_register_gate_parent_hw() macro to allow registering
devres managed gate clocks providing struct clk_hw object as parent.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- none
Changes in v4:
- collected tags
Changes in v3:
- none; this patch is new
include/linux/clk-provider.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 75444e250a78..a49859ef3304 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -622,6 +622,24 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
NULL, (flags), (reg), (bit_idx), \
(clk_gate_flags), (lock))
+/**
+ * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
+ * framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_hw: pointer to parent clk
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \
+ reg, bit_idx, clk_gate_flags, \
+ lock) \
+ __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
+ NULL, (flags), (reg), (bit_idx), \
+ (clk_gate_flags), (lock))
/**
* devm_clk_hw_register_gate_parent_data - register a gate clock with the
* clock framework
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
2024-10-30 11:01 ` [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Claudiu
2024-10-30 11:01 ` [PATCH v5 02/10] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-31 7:48 ` Krzysztof Kozlowski
2024-10-30 11:01 ` [PATCH v5 04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Claudiu
` (8 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
by the RTC. The input to the VBATTB could be a 32KHz crystal
or an external clock device.
The HW block diagram for the clock generator is as follows:
+----------+ XC `\
RTXIN --->| |----->| \ +----+ VBATTCLK
| 32K clock| | |----->|gate|----------->
| osc | XBYP | | +----+
RTXOUT --->| |----->| /
+----------+ ,
After discussions w/ Stephen Boyd the clock tree associated with this
hardware block was exported in Linux as:
vbattb-xtal
xbyp
xc
mux
vbattbclk
where:
- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
- xc, xbyp are mux inputs
- mux is the internal mux
- vbattclk is the gate clock that feeds in the end the RTC
to allow selecting the input of the MUX though assigned-clock DT
properties, using the already existing clock drivers and avoid adding
other DT properties. If the crystal is connected on RTXIN,
RTXOUT pins the XC will be selected as mux input. If an external clock
device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
mux input.
The load capacitance of the internal crystal can be configured
with renesas,vbattb-load-nanofarads DT property.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- collected tags
Changes in v4:
- dropped oscillator from patch description
- s/on-board/internal in patch description
- updated dt-binding included file name in the driver as it has been
renamed to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
- dropped the "_BIT" from driver macros
- used "quartz-load-femtofarads" dt property instead of adding a new one
- register the "vbattclk" as critical clock as this feeds the RTC counter
logic and it needs to stay on from the moment the RTC is configured;
along with it, added a comment to express this.
Changes in v3:
- updated patch description
- dropped dependency on MFD_RENESAS_VBATTB as now there is no
driver built under this flag
- dropped include/clk.h
- added pm_runtime and reset control support
- updated register offsets
- registered 4 clocks: xc, xbyp, mux, vbattclk using generic
clock drivers
- added MODULE_DEVICE_TABLE()
Changes in v2:
- updated patch description
- added vendor name in Kconfig flag
- used cleanup.h lock helpers
- dropped the MFD code
- updated registers offsets
- added vbattb_clk_update_bits() and used it where possible
- added vbattb_clk_need_bypass() to detect the bypass setup necessity
- changed the compatible and driver names
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++
3 files changed, 210 insertions(+)
create mode 100644 drivers/clk/renesas/clk-vbattb.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 76791a1c50ac..4e835a3f1ab4 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -237,6 +237,10 @@ config CLK_RZV2H
bool "RZ/V2H(P) family clock support" if COMPILE_TEST
select RESET_CONTROLLER
+config CLK_RENESAS_VBATTB
+ bool "Renesas VBATTB clock controller"
+ select RESET_CONTROLLER
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 23d2e26051c8..82efaa835ac7 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_CLK_RZV2H) += rzv2h-cpg.o
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o
+obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o
diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c
new file mode 100644
index 000000000000..ff9d1ead455c
--- /dev/null
+++ b/drivers/clk/renesas/clk-vbattb.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * VBATTB clock driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/cleanup.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
+
+#define VBATTB_BKSCCR 0x1c
+#define VBATTB_BKSCCR_SOSEL 6
+#define VBATTB_SOSCCR2 0x24
+#define VBATTB_SOSCCR2_SOSTP2 0
+#define VBATTB_XOSCCR 0x30
+#define VBATTB_XOSCCR_OUTEN 16
+#define VBATTB_XOSCCR_XSEL GENMASK(1, 0)
+#define VBATTB_XOSCCR_XSEL_4_PF 0x0
+#define VBATTB_XOSCCR_XSEL_7_PF 0x1
+#define VBATTB_XOSCCR_XSEL_9_PF 0x2
+#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3
+
+/**
+ * struct vbattb_clk - VBATTB clock data structure
+ * @base: base address
+ * @lock: lock
+ */
+struct vbattb_clk {
+ void __iomem *base;
+ spinlock_t lock;
+};
+
+static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc)
+{
+ switch (of_lc) {
+ case 4000:
+ *reg_lc = VBATTB_XOSCCR_XSEL_4_PF;
+ break;
+ case 7000:
+ *reg_lc = VBATTB_XOSCCR_XSEL_7_PF;
+ break;
+ case 9000:
+ *reg_lc = VBATTB_XOSCCR_XSEL_9_PF;
+ break;
+ case 12500:
+ *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void vbattb_clk_action(void *data)
+{
+ struct device *dev = data;
+ struct reset_control *rstc = dev_get_drvdata(dev);
+ int ret;
+
+ ret = reset_control_assert(rstc);
+ if (ret)
+ dev_err(dev, "Failed to de-assert reset!");
+
+ ret = pm_runtime_put_sync(dev);
+ if (ret < 0)
+ dev_err(dev, "Failed to runtime suspend!");
+
+ of_clk_del_provider(dev->of_node);
+}
+
+static int vbattb_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct clk_parent_data parent_data = {};
+ struct clk_hw_onecell_data *clk_data;
+ const struct clk_hw *parent_hws[2];
+ struct device *dev = &pdev->dev;
+ struct reset_control *rstc;
+ struct vbattb_clk *vbclk;
+ u32 of_lc, reg_lc;
+ struct clk_hw *hw;
+ /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */
+ u8 num_clks = 4;
+ int ret;
+
+ /* Default to 4pF as this is not needed if external clock device is connected. */
+ of_lc = 4000;
+ of_property_read_u32(np, "quartz-load-femtofarads", &of_lc);
+
+ ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc);
+ if (ret)
+ return ret;
+
+ vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL);
+ if (!vbclk)
+ return -ENOMEM;
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+ clk_data->num = num_clks;
+
+ vbclk->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(vbclk->base))
+ return PTR_ERR(vbclk->base);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ rstc = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(rstc);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, rstc);
+ ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev);
+ if (ret)
+ return ret;
+
+ spin_lock_init(&vbclk->lock);
+
+ parent_data.fw_name = "rtx";
+ hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0,
+ vbclk->base + VBATTB_SOSCCR2,
+ VBATTB_SOSCCR2_SOSTP2,
+ CLK_GATE_SET_TO_DISABLE, &vbclk->lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ clk_data->hws[VBATTB_XC] = hw;
+
+ hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ clk_data->hws[VBATTB_XBYP] = hw;
+
+ parent_hws[0] = clk_data->hws[VBATTB_XC];
+ parent_hws[1] = clk_data->hws[VBATTB_XBYP];
+ hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0,
+ vbclk->base + VBATTB_BKSCCR,
+ VBATTB_BKSCCR_SOSEL,
+ 1, 0, &vbclk->lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ clk_data->hws[VBATTB_MUX] = hw;
+
+ /* Set load capacitance before registering the VBATTCLK clock. */
+ scoped_guard(spinlock, &vbclk->lock) {
+ u32 val = readl_relaxed(vbclk->base + VBATTB_XOSCCR);
+
+ val &= ~VBATTB_XOSCCR_XSEL;
+ val |= reg_lc;
+ writel_relaxed(val, vbclk->base + VBATTB_XOSCCR);
+ }
+
+ /* This feeds the RTC counter clock and it needs to stay on. */
+ hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL,
+ vbclk->base + VBATTB_XOSCCR,
+ VBATTB_XOSCCR_OUTEN, 0,
+ &vbclk->lock);
+
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ clk_data->hws[VBATTB_VBATTCLK] = hw;
+
+ return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+}
+
+static const struct of_device_id vbattb_clk_match[] = {
+ { .compatible = "renesas,r9a08g045-vbattb" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, vbattb_clk_match);
+
+static struct platform_driver vbattb_clk_driver = {
+ .driver = {
+ .name = "renesas-vbattb-clk",
+ .of_match_table = vbattb_clk_match,
+ },
+ .probe = vbattb_clk_probe,
+};
+module_platform_driver(vbattb_clk_driver);
+
+MODULE_DESCRIPTION("Renesas VBATTB Clock Driver");
+MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
+MODULE_LICENSE("GPL");
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (2 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 15:43 ` Geert Uytterhoeven
2024-10-30 11:01 ` [PATCH v5 05/10] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Claudiu
` (7 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
The RTC IP available on Renesas RZ/V2H is almost identical with the
one found on Renesas RZ/G3S (it misses the time capture functionality
which is not yet implemented on proposed driver). For this, added also a
generic compatible that will be used at the moment as fallback for both
RZ/G3S and RZ/V2H.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- added back the #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
in example section to fix the build error
- kept the Rb tag from Rob; Rob, please let me know if you consider it
otherwise
Changes in v4:
- collected tags
- dropped the assigned-clocks, assigned-clock-parents properties from the
example, along with r9a08g045-vbattb.h inclusion; these were moved
to the VBATTB example as it fits better in there since these are
related to the VBATTB but not to the RTC;
Rob, I haven't dropped your Rb tag for this; please let me know if you
consider it otherwise.
Changes in v3:
- added RTC bus clock, reset and power-domain; it has been detected
by reverse engineering that RTC and VBATTB clock, reset and power
domain are shared; HW manual doesn't mention it
- updated example with these and with assigned-clock properties
needed to configure the VBATTCLK MUX with proper parent
- updated example section with dt-bindings/clock/r9a08g045-cpg.h
and dt-bindings/clock/r9a08g045-vbattb.h includes
- for all these, dropped Conor's Rb tag
Changes in v2:
- updated patch description and title
- included reference to rtc.yaml
- updated compatible list with a generic compatible as explained in
patch description; with this the node in examples section has also been
updated
- used items to describe interrupts, interrupt-names, clock, clock-names
- updated title section
.../bindings/rtc/renesas,rz-rtca3.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
new file mode 100644
index 000000000000..e70eeb66aa64
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RTCA-3 Real Time Clock
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a08g045-rtca3 # RZ/G3S
+ - const: renesas,rz-rtca3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Alarm interrupt
+ - description: Periodic interrupt
+ - description: Carry interrupt
+
+ interrupt-names:
+ items:
+ - const: alarm
+ - const: period
+ - const: carry
+
+ clocks:
+ items:
+ - description: RTC bus clock
+ - description: RTC counter clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: counter
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: VBATTB module reset
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a08g045-cpg.h>
+ #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ rtc@1004ec00 {
+ compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
+ reg = <0x1004ec00 0x400>;
+ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "alarm", "period", "carry";
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>;
+ clock-names = "bus", "counter";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 05/10] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (3 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 11:01 ` [PATCH v5 06/10] arm64: dts: renesas: r9a08g045: Add VBATTB node Claudiu
` (6 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea,
kernel test robot
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count
mode and binary count mode (selectable though RCR2.CNTMD) capabilities,
alarm capabilities, clock error correction capabilities. It can generate
alarm, period, carry interrupts.
Add a driver for RTCA-3 IP. The driver implements calendar count mode (as
the conversion b/w RTC and system time is simpler, done with bcd2bin(),
bin2bcd()), read and set time, read and set alarm, read and set
an offset.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- populate struct platform_driver::remove instead of
struct platform_driver::remove_new
Changes in v4:
- disabled all interrupts on the initial setup, function rtca3_initial_setup();
RTCA3_RCR1_PIE interrupt (disabled in this series) is used on alarm setup.
- added a comment about the counter clock, when requesting it,
to let others know that this should stay on for the full lifetime of
the RTC
- used RTC_TIMESTAMP_BEGIN_2000 and RTC_TIMESTAMP_BEGIN_2099
- added a comment on rtca3_remove() to mention that the RTC cannot
power on the system
Changes in v3:
- added pm runtime and reset control support; probe() was changed
and rtca3_action() was added as for cleanup; VBATTB and RTC shares
the clock, reset and PM domain; hw manual doesn't specifies
this; it has been detected though reverse engineering
- dropped clk member of struct rtca3_priv as it is used only in
probe()
- renamed rtca3_alarm_irq_enable_helper() to rtca3_alarm_irq_set_helper()
and used it all over the places
- fixed the issue:
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202407191156.wJPjHtKG-lkp@intel.com/
- removed __maybe_unused from suspend/resume function and
use DEFINE_SIMPLE_DEV_PM_OPS() along with pm_ptr()
Changes in v2:
- used cleanup.h helpers for locking
- updated the MAINTAINERS entry with the new name for RTCA-3 documentation
file and a new title (from "RENESAS RZ/G3S RTC DRIVER" to
"RENESAS RTCA-3 RTC DRIVER")
- used 24 hours mode
- changed startup sequence (rtca3_initial_setup()) to avoid stopping
the RTC if it's already configured
- updated the RTC range to 2000-2099
- updated the compatible with the generic one (renesas,rz-rtca3) in the
idea the driver will be also used by the RZ/V2H w/o the necessity to
add a new compatible
MAINTAINERS | 8 +
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-renesas-rtca3.c | 899 ++++++++++++++++++++++++++++++++
4 files changed, 918 insertions(+)
create mode 100644 drivers/rtc/rtc-renesas-rtca3.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 0967064d4fdc..c27e7b5dc80d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19745,6 +19745,14 @@ S: Supported
F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
F: drivers/counter/rz-mtu3-cnt.c
+RENESAS RTCA-3 RTC DRIVER
+M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+L: linux-rtc@vger.kernel.org
+L: linux-renesas-soc@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
+F: drivers/rtc/rtc-renesas-rtca3.c
+
RENESAS RZ/N1 A5PSW SWITCH DRIVER
M: Clément Léger <clement.leger@bootlin.com>
L: linux-renesas-soc@vger.kernel.org
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 66eb1122248b..5c003c0c2f7a 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -2005,6 +2005,16 @@ config RTC_DRV_MA35D1
This driver can also be built as a module, if so, the module
will be called "rtc-ma35d1".
+config RTC_DRV_RENESAS_RTCA3
+ tristate "Renesas RTCA-3 RTC"
+ depends on ARCH_RENESAS
+ help
+ If you say yes here you get support for the Renesas RTCA-3 RTC
+ available on the Renesas RZ/G3S SoC.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-rtca3".
+
comment "HID Sensor RTC drivers"
config RTC_DRV_HID_SENSOR_TIME
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index f62340ecc534..184d2f3cf743 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -158,6 +158,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o
obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o
obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o
obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o
+obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o
obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o
obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o
obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o
diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c
new file mode 100644
index 000000000000..abb0f6f73906
--- /dev/null
+++ b/drivers/rtc/rtc-renesas-rtca3.c
@@ -0,0 +1,899 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * On-Chip RTC Support available on RZ/G3S SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#include <linux/bcd.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/rtc.h>
+
+/* Counter registers. */
+#define RTCA3_RSECCNT 0x2
+#define RTCA3_RSECCNT_SEC GENMASK(6, 0)
+#define RTCA3_RMINCNT 0x4
+#define RTCA3_RMINCNT_MIN GENMASK(6, 0)
+#define RTCA3_RHRCNT 0x6
+#define RTCA3_RHRCNT_HR GENMASK(5, 0)
+#define RTCA3_RHRCNT_PM BIT(6)
+#define RTCA3_RWKCNT 0x8
+#define RTCA3_RWKCNT_WK GENMASK(2, 0)
+#define RTCA3_RDAYCNT 0xa
+#define RTCA3_RDAYCNT_DAY GENMASK(5, 0)
+#define RTCA3_RMONCNT 0xc
+#define RTCA3_RMONCNT_MONTH GENMASK(4, 0)
+#define RTCA3_RYRCNT 0xe
+#define RTCA3_RYRCNT_YEAR GENMASK(7, 0)
+
+/* Alarm registers. */
+#define RTCA3_RSECAR 0x10
+#define RTCA3_RSECAR_SEC GENMASK(6, 0)
+#define RTCA3_RMINAR 0x12
+#define RTCA3_RMINAR_MIN GENMASK(6, 0)
+#define RTCA3_RHRAR 0x14
+#define RTCA3_RHRAR_HR GENMASK(5, 0)
+#define RTCA3_RHRAR_PM BIT(6)
+#define RTCA3_RWKAR 0x16
+#define RTCA3_RWKAR_DAYW GENMASK(2, 0)
+#define RTCA3_RDAYAR 0x18
+#define RTCA3_RDAYAR_DATE GENMASK(5, 0)
+#define RTCA3_RMONAR 0x1a
+#define RTCA3_RMONAR_MON GENMASK(4, 0)
+#define RTCA3_RYRAR 0x1c
+#define RTCA3_RYRAR_YR GENMASK(7, 0)
+#define RTCA3_RYRAREN 0x1e
+
+/* Alarm enable bit (for all alarm registers). */
+#define RTCA3_AR_ENB BIT(7)
+
+/* Control registers. */
+#define RTCA3_RCR1 0x22
+#define RTCA3_RCR1_AIE BIT(0)
+#define RTCA3_RCR1_CIE BIT(1)
+#define RTCA3_RCR1_PIE BIT(2)
+#define RTCA3_RCR1_PES GENMASK(7, 4)
+#define RTCA3_RCR1_PES_1_64_SEC 0x8
+#define RTCA3_RCR2 0x24
+#define RTCA3_RCR2_START BIT(0)
+#define RTCA3_RCR2_RESET BIT(1)
+#define RTCA3_RCR2_AADJE BIT(4)
+#define RTCA3_RCR2_ADJP BIT(5)
+#define RTCA3_RCR2_HR24 BIT(6)
+#define RTCA3_RCR2_CNTMD BIT(7)
+#define RTCA3_RSR 0x20
+#define RTCA3_RSR_AF BIT(0)
+#define RTCA3_RSR_CF BIT(1)
+#define RTCA3_RSR_PF BIT(2)
+#define RTCA3_RADJ 0x2e
+#define RTCA3_RADJ_ADJ GENMASK(5, 0)
+#define RTCA3_RADJ_ADJ_MAX 0x3f
+#define RTCA3_RADJ_PMADJ GENMASK(7, 6)
+#define RTCA3_RADJ_PMADJ_NONE 0
+#define RTCA3_RADJ_PMADJ_ADD 1
+#define RTCA3_RADJ_PMADJ_SUB 2
+
+/* Polling operation timeouts. */
+#define RTCA3_DEFAULT_TIMEOUT_US 150
+#define RTCA3_IRQSET_TIMEOUT_US 5000
+#define RTCA3_START_TIMEOUT_US 150000
+#define RTCA3_RESET_TIMEOUT_US 200000
+
+/**
+ * enum rtca3_alrm_set_step - RTCA3 alarm set steps
+ * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step
+ * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step
+ * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step
+ */
+enum rtca3_alrm_set_step {
+ RTCA3_ALRM_SSTEP_DONE = 0,
+ RTCA3_ALRM_SSTEP_IRQ = 1,
+ RTCA3_ALRM_SSTEP_INIT = 3,
+};
+
+/**
+ * struct rtca3_ppb_per_cycle - PPB per cycle
+ * @ten_sec: PPB per cycle in 10 seconds adjutment mode
+ * @sixty_sec: PPB per cycle in 60 seconds adjustment mode
+ */
+struct rtca3_ppb_per_cycle {
+ int ten_sec;
+ int sixty_sec;
+};
+
+/**
+ * struct rtca3_priv - RTCA3 private data structure
+ * @base: base address
+ * @rtc_dev: RTC device
+ * @rstc: reset control
+ * @set_alarm_completion: alarm setup completion
+ * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step)
+ * @lock: device lock
+ * @ppb: ppb per cycle for each the available adjustment modes
+ * @wakeup_irq: wakeup IRQ
+ */
+struct rtca3_priv {
+ void __iomem *base;
+ struct rtc_device *rtc_dev;
+ struct reset_control *rstc;
+ struct completion set_alarm_completion;
+ atomic_t alrm_sstep;
+ spinlock_t lock;
+ struct rtca3_ppb_per_cycle ppb;
+ int wakeup_irq;
+};
+
+static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val)
+{
+ u8 tmp;
+
+ tmp = readb(priv->base + off);
+ tmp &= ~mask;
+ tmp |= (val & mask);
+ writeb(tmp, priv->base + off);
+}
+
+static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv)
+{
+ u8 val, pending;
+
+ val = readb(priv->base + RTCA3_RSR);
+ pending = val & RTCA3_RSR_AF;
+ writeb(val & ~pending, priv->base + RTCA3_RSR);
+
+ if (pending)
+ rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
+
+ return pending;
+}
+
+static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id)
+{
+ struct rtca3_priv *priv = dev_id;
+ u8 pending;
+
+ guard(spinlock)(&priv->lock);
+
+ pending = rtca3_alarm_handler_helper(priv);
+
+ return IRQ_RETVAL(pending);
+}
+
+static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id)
+{
+ struct rtca3_priv *priv = dev_id;
+ u8 val, pending;
+
+ guard(spinlock)(&priv->lock);
+
+ val = readb(priv->base + RTCA3_RSR);
+ pending = val & RTCA3_RSR_PF;
+
+ if (pending) {
+ writeb(val & ~pending, priv->base + RTCA3_RSR);
+
+ if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) {
+ /* Alarm setup in progress. */
+ atomic_dec(&priv->alrm_sstep);
+
+ if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) {
+ /*
+ * We got 2 * 1/64 periodic interrupts. Disable
+ * interrupt and let alarm setup continue.
+ */
+ rtca3_byte_update_bits(priv, RTCA3_RCR1,
+ RTCA3_RCR1_PIE, 0);
+ readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val,
+ !(val & RTCA3_RCR1_PIE),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ complete(&priv->set_alarm_completion);
+ }
+ }
+ }
+
+ return IRQ_RETVAL(pending);
+}
+
+static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt)
+{
+ /* Offset b/w time and alarm registers. */
+ u8 offset = cnt ? 0 : 0xe;
+
+ /*
+ * According to HW manual (section 22.6.4. Notes on writing to and
+ * reading from registers) after writing to count registers, alarm
+ * registers, year alarm enable register, bits RCR2.AADJE, AADJP,
+ * and HR24 register, we need to do 3 empty reads before being
+ * able to fetch the registers content.
+ */
+ for (u8 i = 0; i < 3; i++) {
+ readb(priv->base + RTCA3_RSECCNT + offset);
+ readb(priv->base + RTCA3_RMINCNT + offset);
+ readb(priv->base + RTCA3_RHRCNT + offset);
+ readb(priv->base + RTCA3_RWKCNT + offset);
+ readb(priv->base + RTCA3_RDAYCNT + offset);
+ readw(priv->base + RTCA3_RYRCNT + offset);
+ if (!cnt)
+ readb(priv->base + RTCA3_RYRAREN);
+ }
+}
+
+static int rtca3_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ u8 sec, min, hour, wday, mday, month, tmp;
+ u8 trials = 0;
+ u32 year100;
+ u16 year;
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ tmp = readb(priv->base + RTCA3_RCR2);
+ if (!(tmp & RTCA3_RCR2_START))
+ return -EINVAL;
+
+ do {
+ /* Clear carry interrupt. */
+ rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0);
+
+ /* Read counters. */
+ sec = readb(priv->base + RTCA3_RSECCNT);
+ min = readb(priv->base + RTCA3_RMINCNT);
+ hour = readb(priv->base + RTCA3_RHRCNT);
+ wday = readb(priv->base + RTCA3_RWKCNT);
+ mday = readb(priv->base + RTCA3_RDAYCNT);
+ month = readb(priv->base + RTCA3_RMONCNT);
+ year = readw(priv->base + RTCA3_RYRCNT);
+
+ tmp = readb(priv->base + RTCA3_RSR);
+
+ /*
+ * We cannot generate carries due to reading 64Hz counter as
+ * the driver doesn't implement carry, thus, carries will be
+ * generated once per seconds. Add a timeout of 5 trials here
+ * to avoid infinite loop, if any.
+ */
+ } while ((tmp & RTCA3_RSR_CF) && ++trials < 5);
+
+ if (trials >= 5)
+ return -ETIMEDOUT;
+
+ tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec));
+ tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min));
+ tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour));
+ tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday));
+ tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday));
+ tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1;
+ year = FIELD_GET(RTCA3_RYRCNT_YEAR, year);
+ year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
+ tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
+
+ return 0;
+}
+
+static int rtca3_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ u8 rcr2, tmp;
+ int ret;
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ /* Stop the RTC. */
+ rcr2 = readb(priv->base + RTCA3_RCR2);
+ writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
+ ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
+ !(tmp & RTCA3_RCR2_START),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ /* Update time. */
+ writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT);
+ writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT);
+ writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT);
+ writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT);
+ writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT);
+ writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT);
+ writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT);
+
+ /* Make sure we can read back the counters. */
+ rtca3_prepare_cntalrm_regs_for_read(priv, true);
+
+ /* Start RTC. */
+ writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
+ return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
+ (tmp & RTCA3_RCR2_START),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+}
+
+static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv,
+ u8 interrupts,
+ unsigned int enabled)
+{
+ u8 tmp, val;
+
+ if (enabled) {
+ /*
+ * AIE, CIE, PIE bit indexes in RSR corresponds with
+ * those on RCR1. Same interrupts mask can be used.
+ */
+ rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0);
+ val = interrupts;
+ } else {
+ val = 0;
+ }
+
+ rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val);
+ return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
+ ((tmp & interrupts) == val),
+ 10, RTCA3_IRQSET_TIMEOUT_US);
+}
+
+static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ return rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled);
+}
+
+static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ u8 sec, min, hour, wday, mday, month;
+ struct rtc_time *tm = &wkalrm->time;
+ u32 year100;
+ u16 year;
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ sec = readb(priv->base + RTCA3_RSECAR);
+ min = readb(priv->base + RTCA3_RMINAR);
+ hour = readb(priv->base + RTCA3_RHRAR);
+ wday = readb(priv->base + RTCA3_RWKAR);
+ mday = readb(priv->base + RTCA3_RDAYAR);
+ month = readb(priv->base + RTCA3_RMONAR);
+ year = readw(priv->base + RTCA3_RYRAR);
+
+ tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec));
+ tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min));
+ tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour));
+ tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday));
+ tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday));
+ tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1;
+ year = FIELD_GET(RTCA3_RYRAR_YR, year);
+ year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
+ tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
+
+ wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE);
+
+ return 0;
+}
+
+static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ struct rtc_time *tm = &wkalrm->time;
+ u8 rcr1, tmp;
+ int ret;
+
+ scoped_guard(spinlock_irqsave, &priv->lock) {
+ tmp = readb(priv->base + RTCA3_RCR2);
+ if (!(tmp & RTCA3_RCR2_START))
+ return -EPERM;
+
+ /* Disable AIE to prevent false interrupts. */
+ rcr1 = readb(priv->base + RTCA3_RCR1);
+ rcr1 &= ~RTCA3_RCR1_AIE;
+ writeb(rcr1, priv->base + RTCA3_RCR1);
+ ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
+ !(tmp & RTCA3_RCR1_AIE),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ /* Set the time and enable the alarm. */
+ writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR);
+ writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR);
+ writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR);
+ writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR);
+ writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR);
+ writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR);
+
+ writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR);
+ writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN);
+
+ /* Make sure we can read back the counters. */
+ rtca3_prepare_cntalrm_regs_for_read(priv, false);
+
+ /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */
+ atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT);
+ reinit_completion(&priv->set_alarm_completion);
+
+ /* Enable periodic interrupt. */
+ rcr1 |= RTCA3_RCR1_PIE;
+ writeb(rcr1, priv->base + RTCA3_RCR1);
+ ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
+ (tmp & RTCA3_RCR1_PIE),
+ 10, RTCA3_IRQSET_TIMEOUT_US);
+ }
+
+ if (ret)
+ goto setup_failed;
+
+ /* Wait for the 2 * 1/64 periodic interrupts. */
+ ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion,
+ msecs_to_jiffies(500));
+ if (ret <= 0) {
+ ret = -ETIMEDOUT;
+ goto setup_failed;
+ }
+
+ scoped_guard(spinlock_irqsave, &priv->lock) {
+ ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled);
+ atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
+ }
+
+ return ret;
+
+setup_failed:
+ scoped_guard(spinlock_irqsave, &priv->lock) {
+ /*
+ * Disable PIE to avoid interrupt storm in case HW needed more than
+ * specified timeout for setup.
+ */
+ writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1);
+ readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
+ }
+
+ return ret;
+}
+
+static int rtca3_read_offset(struct device *dev, long *offset)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ u8 val, radj, cycles;
+ u32 ppb_per_cycle;
+
+ scoped_guard(spinlock_irqsave, &priv->lock) {
+ radj = readb(priv->base + RTCA3_RADJ);
+ val = readb(priv->base + RTCA3_RCR2);
+ }
+
+ cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj);
+
+ if (!cycles) {
+ *offset = 0;
+ return 0;
+ }
+
+ if (val & RTCA3_RCR2_ADJP)
+ ppb_per_cycle = priv->ppb.ten_sec;
+ else
+ ppb_per_cycle = priv->ppb.sixty_sec;
+
+ *offset = cycles * ppb_per_cycle;
+ val = FIELD_GET(RTCA3_RADJ_PMADJ, radj);
+ if (val == RTCA3_RADJ_PMADJ_SUB)
+ *offset = -(*offset);
+
+ return 0;
+}
+
+static int rtca3_set_offset(struct device *dev, long offset)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ int cycles, cycles10, cycles60;
+ u8 radj, adjp, tmp;
+ int ret;
+
+ /*
+ * Automatic time error adjustment could be set at intervals of 10
+ * or 60 seconds.
+ */
+ cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec);
+ cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec);
+
+ /* We can set b/w 1 and 63 clock cycles. */
+ if (cycles60 >= -RTCA3_RADJ_ADJ_MAX &&
+ cycles60 <= RTCA3_RADJ_ADJ_MAX) {
+ cycles = cycles60;
+ adjp = 0;
+ } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX &&
+ cycles10 <= RTCA3_RADJ_ADJ_MAX) {
+ cycles = cycles10;
+ adjp = RTCA3_RCR2_ADJP;
+ } else {
+ return -ERANGE;
+ }
+
+ radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles));
+ if (!cycles)
+ radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE);
+ else if (cycles > 0)
+ radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD);
+ else
+ radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB);
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ tmp = readb(priv->base + RTCA3_RCR2);
+
+ if ((tmp & RTCA3_RCR2_ADJP) != adjp) {
+ /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */
+ writeb(0, priv->base + RTCA3_RADJ);
+ ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp,
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp);
+ ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
+ ((tmp & RTCA3_RCR2_ADJP) == adjp),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ if (ret)
+ return ret;
+ }
+
+ writeb(radj, priv->base + RTCA3_RADJ);
+ return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+}
+
+static const struct rtc_class_ops rtca3_ops = {
+ .read_time = rtca3_read_time,
+ .set_time = rtca3_set_time,
+ .read_alarm = rtca3_read_alarm,
+ .set_alarm = rtca3_set_alarm,
+ .alarm_irq_enable = rtca3_alarm_irq_enable,
+ .set_offset = rtca3_set_offset,
+ .read_offset = rtca3_read_offset,
+};
+
+static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv)
+{
+ unsigned long osc32k_rate;
+ u8 val, tmp, mask;
+ u32 sleep_us;
+ int ret;
+
+ osc32k_rate = clk_get_rate(clk);
+ if (!osc32k_rate)
+ return -EINVAL;
+
+ sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6;
+
+ priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10));
+ priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60));
+
+ /*
+ * According to HW manual (section 22.4.2. Clock and count mode setting procedure)
+ * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled.
+ */
+ usleep_range(sleep_us, sleep_us + 10);
+
+ /* Disable all interrupts. */
+ mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE;
+ ret = rtca3_alarm_irq_set_helper(priv, mask, 0);
+ if (ret)
+ return ret;
+
+ mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24;
+ val = readb(priv->base + RTCA3_RCR2);
+ /* Nothing to do if already started in 24 hours and calendar count mode. */
+ if ((val & mask) == mask)
+ return 0;
+
+ /* Reconfigure the RTC in 24 hours and calendar count mode. */
+ mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD;
+ writeb(0, priv->base + RTCA3_RCR2);
+ ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ /*
+ * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control
+ * Register 2) this needs to be done separate from stop operation.
+ */
+ mask = RTCA3_RCR2_HR24;
+ val = RTCA3_RCR2_HR24;
+ writeb(val, priv->base + RTCA3_RCR2);
+ ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ /* Execute reset. */
+ mask = RTCA3_RCR2_RESET;
+ writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2);
+ ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
+ 10, RTCA3_RESET_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ /*
+ * According to HW manual (section 22.6.3. Notes on writing to and reading
+ * from registers) after reset we need to wait 6 clock cycles before
+ * writing to RTC registers.
+ */
+ usleep_range(sleep_us, sleep_us + 10);
+
+ /* Set no adjustment. */
+ writeb(0, priv->base + RTCA3_RADJ);
+ ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
+ RTCA3_DEFAULT_TIMEOUT_US);
+
+ /* Start the RTC and enable automatic time error adjustment. */
+ mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
+ val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
+ writeb(val, priv->base + RTCA3_RCR2);
+ ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
+ 10, RTCA3_START_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ /*
+ * According to HW manual (section 22.6.4. Notes on writing to and reading
+ * from registers) we need to wait 1/128 seconds while the clock is operating
+ * (RCR2.START bit = 1) to be able to read the counters after a return from
+ * reset.
+ */
+ usleep_range(8000, 9000);
+
+ /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */
+ val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC);
+ rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val);
+ return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val),
+ 10, RTCA3_DEFAULT_TIMEOUT_US);
+}
+
+static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ int ret, irq;
+
+ irq = platform_get_irq_byname(pdev, "alarm");
+ if (irq < 0)
+ return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n");
+
+ ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n");
+ priv->wakeup_irq = irq;
+
+ irq = platform_get_irq_byname(pdev, "period");
+ if (irq < 0)
+ return dev_err_probe(dev, irq, "Failed to get period IRQ!\n");
+
+ ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request period IRQ!\n");
+
+ /*
+ * Driver doesn't implement carry handler. Just get the IRQ here
+ * for backward compatibility, in case carry support will be added later.
+ */
+ irq = platform_get_irq_byname(pdev, "carry");
+ if (irq < 0)
+ return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n");
+
+ return 0;
+}
+
+static void rtca3_action(void *data)
+{
+ struct device *dev = data;
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+ int ret;
+
+ ret = reset_control_assert(priv->rstc);
+ if (ret)
+ dev_err(dev, "Failed to de-assert reset!");
+
+ ret = pm_runtime_put_sync(dev);
+ if (ret < 0)
+ dev_err(dev, "Failed to runtime suspend!");
+}
+
+static int rtca3_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rtca3_priv *priv;
+ struct clk *clk;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ priv->rstc = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return PTR_ERR(priv->rstc);
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(priv->rstc);
+ if (ret) {
+ pm_runtime_put_sync(dev);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, priv);
+ ret = devm_add_action_or_reset(dev, rtca3_action, dev);
+ if (ret)
+ return ret;
+
+ /*
+ * This must be an always-on clock to keep the RTC running even after
+ * driver is unbinded.
+ */
+ clk = devm_clk_get_enabled(dev, "counter");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ spin_lock_init(&priv->lock);
+ atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
+ init_completion(&priv->set_alarm_completion);
+
+ ret = rtca3_initial_setup(clk, priv);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to setup the RTC!\n");
+
+ ret = rtca3_request_irqs(pdev, priv);
+ if (ret)
+ return ret;
+
+ device_init_wakeup(&pdev->dev, 1);
+
+ priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
+ if (IS_ERR(priv->rtc_dev))
+ return PTR_ERR(priv->rtc_dev);
+
+ priv->rtc_dev->ops = &rtca3_ops;
+ priv->rtc_dev->max_user_freq = 256;
+ priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
+ priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
+
+ return devm_rtc_register_device(priv->rtc_dev);
+}
+
+static void rtca3_remove(struct platform_device *pdev)
+{
+ struct rtca3_priv *priv = platform_get_drvdata(pdev);
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ /*
+ * Disable alarm, periodic interrupts. The RTC device cannot
+ * power up the system.
+ */
+ rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE | RTCA3_RCR1_PIE, 0);
+}
+
+static int rtca3_suspend(struct device *dev)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+
+ if (!device_may_wakeup(dev))
+ return 0;
+
+ /* Alarm setup in progress. */
+ if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE)
+ return -EBUSY;
+
+ enable_irq_wake(priv->wakeup_irq);
+
+ return 0;
+}
+
+static int rtca3_clean_alarm(struct rtca3_priv *priv)
+{
+ struct rtc_device *rtc_dev = priv->rtc_dev;
+ time64_t alarm_time, now;
+ struct rtc_wkalrm alarm;
+ struct rtc_time tm;
+ u8 pending;
+ int ret;
+
+ ret = rtc_read_alarm(rtc_dev, &alarm);
+ if (ret)
+ return ret;
+
+ if (!alarm.enabled)
+ return 0;
+
+ ret = rtc_read_time(rtc_dev, &tm);
+ if (ret)
+ return ret;
+
+ alarm_time = rtc_tm_to_time64(&alarm.time);
+ now = rtc_tm_to_time64(&tm);
+ if (alarm_time >= now)
+ return 0;
+
+ /*
+ * Heuristically, it has been determined that when returning from deep
+ * sleep state the RTCA3_RSR.AF is zero even though the alarm expired.
+ * Call again the rtc_update_irq() if alarm helper detects this.
+ */
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ pending = rtca3_alarm_handler_helper(priv);
+ if (!pending)
+ rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
+
+ return 0;
+}
+
+static int rtca3_resume(struct device *dev)
+{
+ struct rtca3_priv *priv = dev_get_drvdata(dev);
+
+ if (!device_may_wakeup(dev))
+ return 0;
+
+ disable_irq_wake(priv->wakeup_irq);
+
+ /*
+ * According to the HW manual (section 22.6.4 Notes on writing to
+ * and reading from registers) we need to wait 1/128 seconds while
+ * RCR2.START = 1 to be able to read the counters after a return from low
+ * power consumption state.
+ */
+ mdelay(8);
+
+ /*
+ * The alarm cannot wake the system from deep sleep states. In case
+ * we return from deep sleep states and the alarm expired we need
+ * to disable it to avoid failures when setting another alarm.
+ */
+ return rtca3_clean_alarm(priv);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
+
+static const struct of_device_id rtca3_of_match[] = {
+ { .compatible = "renesas,rz-rtca3", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rtca3_of_match);
+
+static struct platform_driver rtca3_platform_driver = {
+ .driver = {
+ .name = "rtc-rtca3",
+ .pm = pm_ptr(&rtca3_pm_ops),
+ .of_match_table = rtca3_of_match,
+ },
+ .probe = rtca3_probe,
+ .remove = rtca3_remove,
+};
+module_platform_driver(rtca3_platform_driver);
+
+MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver");
+MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
+MODULE_LICENSE("GPL");
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 06/10] arm64: dts: renesas: r9a08g045: Add VBATTB node
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (4 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 05/10] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 11:01 ` [PATCH v5 07/10] arm64: dts: renesas: r9a08g045: Add RTC node Claudiu
` (5 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add the DT node for the VBATTB IP along with DT bindings for the clock
it provides.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- dropped the status = "disabled"; for the vbattb-xtal node
Changes in v4:
- used clock-controller for the vbattb node name
- move the node near scif0 for ordering
- set the vbattb_xtal status as disabled to avoid having it exported
in linux with frequency = 0 in boards that don't use it
- collected tags
Changes in v3:
- dropped the child nodes of vbattb; along with this dropped ranges,
interrupt-names, #address-cells, #size-cells
- added vbattb_xtal as input clock for vbattb
Changes in v2:
- update compatibles
- updated clocks and clock-names for clock-controller node
- removed the power domain from the clock-controller as this is
controlled by parent node in v2
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 067a26a66c24..a1d5084b074a 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -72,6 +72,18 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ vbattb: clock-controller@1005c000 {
+ compatible = "renesas,r9a08g045-vbattb";
+ reg = <0 0x1005c000 0 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+ clock-names = "bclk", "rtx";
+ #clock-cells = <1>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ status = "disabled";
+ };
+
i2c0: i2c@10090000 {
compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
reg = <0 0x10090000 0 0x400>;
@@ -425,4 +437,11 @@ timer {
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
+
+ vbattb_xtal: vbattb-xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
};
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 07/10] arm64: dts: renesas: r9a08g045: Add RTC node
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (5 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 06/10] arm64: dts: renesas: r9a08g045: Add VBATTB node Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 11:01 ` [PATCH v5 08/10] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Claudiu
` (4 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- collected tags
Changes in v4:
- dropped the assigned-clocks, assigned-clock-parents properties as they
fit better on vbattb node
- moved the RTC close to serial node for ordering
Changes in v3:
- added CPG clock, power domain, reset
- and assigned-clocks, assigned-clock-parents to configure the
VBATTCLK
- included dt-bindings/clock/r9a08g045-vbattb.h
Changes in v2:
- updated compatibles
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index a1d5084b074a..be8a0a768c65 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a08g045-cpg.h>
+#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
/ {
compatible = "renesas,r9a08g045";
@@ -72,6 +73,20 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ rtc: rtc@1004ec00 {
+ compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
+ reg = <0 0x1004ec00 0 0x400>;
+ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "alarm", "period", "carry";
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
+ clock-names = "bus", "counter";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ status = "disabled";
+ };
+
vbattb: clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0 0x1005c000 0 0x1000>;
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 08/10] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (6 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 07/10] arm64: dts: renesas: r9a08g045: Add RTC node Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 11:01 ` [PATCH v5 09/10] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Claudiu
` (3 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Enable the VBATTB controller. It provides the clock for RTC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- dropped the status = "okay"; from vbattb_xtal node
Changes in v4:
- added assigned-clocks, assigned-clock-parents properties
- set vbattb_xtal status = "okay"
- collected tags
Changes in v3:
- updated patch description
- dropped vbattclk
- added renesas,vbattb-load-nanofarads on vbattb
- moved vbattb before vbattb_xtal
Changes in v2:
- none
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 71424e69939e..30bb4f5a7dfd 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2023 Renesas Electronics Corp.
*/
+#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
@@ -344,6 +345,17 @@ mux {
};
};
+&vbattb {
+ assigned-clocks = <&vbattb VBATTB_MUX>;
+ assigned-clock-parents = <&vbattb VBATTB_XC>;
+ quartz-load-femtofarads = <12500>;
+ status = "okay";
+};
+
+&vbattb_xtal {
+ clock-frequency = <32768>;
+};
+
&wdt0 {
timeout-sec = <60>;
status = "okay";
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 09/10] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (7 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 08/10] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-30 11:01 ` [PATCH v5 10/10] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Claudiu
` (2 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Enable RTC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- none
Changes in v4:
- collected tags
Changes in v3:
- none
Changes in v2:
- none
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 30bb4f5a7dfd..2ed01d391554 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -345,6 +345,10 @@ mux {
};
};
+&rtc {
+ status = "okay";
+};
+
&vbattb {
assigned-clocks = <&vbattb VBATTB_MUX>;
assigned-clock-parents = <&vbattb VBATTB_XC>;
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 10/10] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (8 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 09/10] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Claudiu
@ 2024-10-30 11:01 ` Claudiu
2024-10-31 7:47 ` Krzysztof Kozlowski
2024-10-30 15:50 ` [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Geert Uytterhoeven
2024-10-31 23:17 ` (subset) " Alexandre Belloni
11 siblings, 1 reply; 23+ messages in thread
From: Claudiu @ 2024-10-30 11:01 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are
available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for
the RTC counter.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v5:
- none
Changes in v4:
- squashed w/ patch "arm64: defconfig: Enable Renesas RTCA-3 flag" from v3
- updated patch description
- collected tags
Changes in v3:
- update patch title and description
- dropped CONFIG_MFD_RENESAS_VBATTB
Changes in v2:
- added CONFIG_MFD_RENESAS_VBATTB
- added vendor name in the VBATTB clock flag
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0fad83642034..4f4fe8d9125c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1222,6 +1222,7 @@ CONFIG_RTC_DRV_IMX_SC=m
CONFIG_RTC_DRV_MT6397=m
CONFIG_RTC_DRV_XGENE=y
CONFIG_RTC_DRV_TI_K3=m
+CONFIG_RTC_DRV_RENESAS_RTCA3=y
CONFIG_DMADEVICES=y
CONFIG_DMA_BCM2835=y
CONFIG_DMA_SUN6I=m
@@ -1371,6 +1372,7 @@ CONFIG_SM_VIDEOCC_8250=y
CONFIG_QCOM_HFPLL=y
CONFIG_CLK_GFM_LPASS_SM8250=m
CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
+CONFIG_CLK_RENESAS_VBATTB=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_TEGRA186_TIMER=y
--
2.39.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v5 04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP
2024-10-30 11:01 ` [PATCH v5 04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Claudiu
@ 2024-10-30 15:43 ` Geert Uytterhoeven
0 siblings, 0 replies; 23+ messages in thread
From: Geert Uytterhoeven @ 2024-10-30 15:43 UTC (permalink / raw)
To: Claudiu
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, alexandre.belloni,
magnus.damm, p.zabel, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, linux-rtc, linux-arm-kernel, Claudiu Beznea
On Wed, Oct 30, 2024 at 12:01 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
> The RTC IP available on Renesas RZ/V2H is almost identical with the
> one found on Renesas RZ/G3S (it misses the time capture functionality
> which is not yet implemented on proposed driver). For this, added also a
> generic compatible that will be used at the moment as fallback for both
> RZ/G3S and RZ/V2H.
>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v5:
> - added back the #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
> in example section to fix the build error
> - kept the Rb tag from Rob; Rob, please let me know if you consider it
> otherwise
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (9 preceding siblings ...)
2024-10-30 11:01 ` [PATCH v5 10/10] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Claudiu
@ 2024-10-30 15:50 ` Geert Uytterhoeven
2024-10-30 18:56 ` Alexandre Belloni
2024-10-31 23:17 ` (subset) " Alexandre Belloni
11 siblings, 1 reply; 23+ messages in thread
From: Geert Uytterhoeven @ 2024-10-30 15:50 UTC (permalink / raw)
To: mturquette, sboyd, alexandre.belloni
Cc: Claudiu, robh, krzk+dt, conor+dt, magnus.damm, p.zabel,
linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, Claudiu Beznea
Hi Mike, Stephen, Alexander,
On Wed, Oct 30, 2024 at 12:01 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> On the Renesas RZ/G3S SoC the RTC clock is provided by the VBATTB
> IP. A 32 KHz crystall oscillator could be connected to the VBATTB
> input pins. The logic to control this clock (and pass it to RTC)
> is inside the VBATTB IP. For this, the clk-vbattb driver was added
> (patches 01-03/12).
>
> Patches:
> - 01-03/10: add VBATTB support that provides the RTC clock
> - 04-05/10: add the RTC driver
> - 06-09/10: update the device trees with proper nodes to enable RTC
> - 10/10: enable proper config flags for RTC to work on RZ/G3S SoC
>
> Merge strategy, if any:
> - clock patches (01-03/10) need to go though the same tree because of
> patch 03/10 using the devm_clk_hw_register_gate_parent_hw() introduced
> in patch 02/12
Once Mike/Stephen are happy with 02, I can queue patches 01-03 in
renesas-clk.
> - RTC patches (04-05/10) can go though RTC tree
> - DTS and defconfig patches can go though Renesas tree
Patches 06 and 08 I can queue in renesas-devel soon.
For 07 and 09, I am waiting for feedback from Alexandre on the RTC
DT bindings.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC
2024-10-30 15:50 ` [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Geert Uytterhoeven
@ 2024-10-30 18:56 ` Alexandre Belloni
0 siblings, 0 replies; 23+ messages in thread
From: Alexandre Belloni @ 2024-10-30 18:56 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: mturquette, sboyd, Claudiu, robh, krzk+dt, conor+dt, magnus.damm,
p.zabel, linux-renesas-soc, linux-clk, devicetree, linux-kernel,
linux-rtc, linux-arm-kernel, Claudiu Beznea
On 30/10/2024 16:50:43+0100, Geert Uytterhoeven wrote:
> Hi Mike, Stephen, Alexander,
>
> On Wed, Oct 30, 2024 at 12:01 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > On the Renesas RZ/G3S SoC the RTC clock is provided by the VBATTB
> > IP. A 32 KHz crystall oscillator could be connected to the VBATTB
> > input pins. The logic to control this clock (and pass it to RTC)
> > is inside the VBATTB IP. For this, the clk-vbattb driver was added
> > (patches 01-03/12).
> >
> > Patches:
> > - 01-03/10: add VBATTB support that provides the RTC clock
> > - 04-05/10: add the RTC driver
> > - 06-09/10: update the device trees with proper nodes to enable RTC
> > - 10/10: enable proper config flags for RTC to work on RZ/G3S SoC
> >
> > Merge strategy, if any:
> > - clock patches (01-03/10) need to go though the same tree because of
> > patch 03/10 using the devm_clk_hw_register_gate_parent_hw() introduced
> > in patch 02/12
>
> Once Mike/Stephen are happy with 02, I can queue patches 01-03 in
> renesas-clk.
>
> > - RTC patches (04-05/10) can go though RTC tree
> > - DTS and defconfig patches can go though Renesas tree
>
> Patches 06 and 08 I can queue in renesas-devel soon.
> For 07 and 09, I am waiting for feedback from Alexandre on the RTC
> DT bindings.
I'll take 4 and 5 this cycle.
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 02/10] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw()
2024-10-30 11:01 ` [PATCH v5 02/10] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Claudiu
@ 2024-10-30 19:47 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2024-10-30 19:47 UTC (permalink / raw)
To: Claudiu, alexandre.belloni, conor+dt, geert+renesas, krzk+dt,
magnus.damm, mturquette, p.zabel, robh
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, claudiu.beznea, Claudiu Beznea
Subject can just be "clk: Add devm_clk_hw_register_gate_parent_hw()"
Quoting Claudiu (2024-10-30 04:01:12)
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add devm_clk_hw_register_gate_parent_hw() macro to allow registering
> devres managed gate clocks providing struct clk_hw object as parent.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
2024-10-30 11:01 ` [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Claudiu
@ 2024-10-31 7:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 23+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 7:46 UTC (permalink / raw)
To: Claudiu
Cc: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel, linux-renesas-soc,
linux-clk, devicetree, linux-kernel, linux-rtc, linux-arm-kernel,
Claudiu Beznea
On Wed, Oct 30, 2024 at 01:01:11PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
> the tamper detector and a small general usage memory of 128B.
>
> The VBATTB controller controls the clock for the RTC on the Renesas
> RZ/G3S. The HW block diagram for the clock logic is as follows:
>
> +----------+ XC `\
> RTXIN --->| |----->| \ +----+ VBATTCLK
> | 32K clock| | |----->|gate|----------->
> | osc | XBYP | | +----+
> RTXOUT --->| |----->| /
> +----------+ ,/
>
> One could connect as input to this HW block either a crystal or
> an external clock device. This is board specific.
>
> After discussions w/ Stephen Boyd the clock tree associated with this
> hardware block was exported in Linux as:
>
> input-xtal
> xbyp
> xc
> mux
> vbattclk
>
> where:
> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
> - xc, xbyp are mux inputs
> - mux is the internal mux
> - vbattclk is the gate clock that feeds in the end the RTC
>
> to allow selecting the input of the MUX though assigned-clock DT
> properties, using the already existing clock drivers and avoid adding
> other DT properties.
>
> This allows select the input of the mux based on the type of the
> connected input clock:
> - if the 32768 crystal is connected as input for the VBATTB,
> the input of the mux should be xc
> - if an external clock device is connected as input for the VBATTB the
> input of the mux should be xbyp
>
> Add bindings for the VBATTB controller.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v5:
> - used spaces in the diagram from the patch description
> - added "This is board specific" in the board description to emphasize
> the usage of the assigned-clocks in the example
> - added default for quartz-load-femtofarads
> - collected tags
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 10/10] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags
2024-10-30 11:01 ` [PATCH v5 10/10] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Claudiu
@ 2024-10-31 7:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 23+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 7:47 UTC (permalink / raw)
To: Claudiu
Cc: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel, linux-renesas-soc,
linux-clk, devicetree, linux-kernel, linux-rtc, linux-arm-kernel,
Claudiu Beznea
On Wed, Oct 30, 2024 at 01:01:20PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are
> available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for
> the RTC counter.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v5:
> - none
>
> Changes in v4:
> - squashed w/ patch "arm64: defconfig: Enable Renesas RTCA-3 flag" from v3
> - updated patch description
> - collected tags
>
> Changes in v3:
> - update patch title and description
> - dropped CONFIG_MFD_RENESAS_VBATTB
>
> Changes in v2:
> - added CONFIG_MFD_RENESAS_VBATTB
> - added vendor name in the VBATTB clock flag
>
> arch/arm64/configs/defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 0fad83642034..4f4fe8d9125c 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1222,6 +1222,7 @@ CONFIG_RTC_DRV_IMX_SC=m
> CONFIG_RTC_DRV_MT6397=m
> CONFIG_RTC_DRV_XGENE=y
> CONFIG_RTC_DRV_TI_K3=m
> +CONFIG_RTC_DRV_RENESAS_RTCA3=y
This should be module.
> CONFIG_DMADEVICES=y
> CONFIG_DMA_BCM2835=y
> CONFIG_DMA_SUN6I=m
> @@ -1371,6 +1372,7 @@ CONFIG_SM_VIDEOCC_8250=y
> CONFIG_QCOM_HFPLL=y
> CONFIG_CLK_GFM_LPASS_SM8250=m
> CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
> +CONFIG_CLK_RENESAS_VBATTB=y
This as well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver
2024-10-30 11:01 ` [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver Claudiu
@ 2024-10-31 7:48 ` Krzysztof Kozlowski
2024-10-31 8:43 ` Geert Uytterhoeven
0 siblings, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 7:48 UTC (permalink / raw)
To: Claudiu
Cc: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel, linux-renesas-soc,
linux-clk, devicetree, linux-kernel, linux-rtc, linux-arm-kernel,
Claudiu Beznea
On Wed, Oct 30, 2024 at 01:01:13PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
> by the RTC. The input to the VBATTB could be a 32KHz crystal
> or an external clock device.
>
> The HW block diagram for the clock generator is as follows:
>
> +----------+ XC `\
> RTXIN --->| |----->| \ +----+ VBATTCLK
> | 32K clock| | |----->|gate|----------->
> | osc | XBYP | | +----+
> RTXOUT --->| |----->| /
> +----------+ ,
>
> After discussions w/ Stephen Boyd the clock tree associated with this
> hardware block was exported in Linux as:
>
> vbattb-xtal
> xbyp
> xc
> mux
> vbattbclk
>
> where:
> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
> - xc, xbyp are mux inputs
> - mux is the internal mux
> - vbattclk is the gate clock that feeds in the end the RTC
>
> to allow selecting the input of the MUX though assigned-clock DT
> properties, using the already existing clock drivers and avoid adding
> other DT properties. If the crystal is connected on RTXIN,
> RTXOUT pins the XC will be selected as mux input. If an external clock
> device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
> mux input.
>
> The load capacitance of the internal crystal can be configured
> with renesas,vbattb-load-nanofarads DT property.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v5:
> - collected tags
>
> Changes in v4:
> - dropped oscillator from patch description
> - s/on-board/internal in patch description
> - updated dt-binding included file name in the driver as it has been
> renamed to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
> - dropped the "_BIT" from driver macros
> - used "quartz-load-femtofarads" dt property instead of adding a new one
> - register the "vbattclk" as critical clock as this feeds the RTC counter
> logic and it needs to stay on from the moment the RTC is configured;
> along with it, added a comment to express this.
>
> Changes in v3:
> - updated patch description
> - dropped dependency on MFD_RENESAS_VBATTB as now there is no
> driver built under this flag
> - dropped include/clk.h
> - added pm_runtime and reset control support
> - updated register offsets
> - registered 4 clocks: xc, xbyp, mux, vbattclk using generic
> clock drivers
> - added MODULE_DEVICE_TABLE()
>
> Changes in v2:
> - updated patch description
> - added vendor name in Kconfig flag
> - used cleanup.h lock helpers
> - dropped the MFD code
> - updated registers offsets
> - added vbattb_clk_update_bits() and used it where possible
> - added vbattb_clk_need_bypass() to detect the bypass setup necessity
> - changed the compatible and driver names
>
>
> drivers/clk/renesas/Kconfig | 4 +
> drivers/clk/renesas/Makefile | 1 +
> drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++
> 3 files changed, 210 insertions(+)
> create mode 100644 drivers/clk/renesas/clk-vbattb.c
>
> diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
> index 76791a1c50ac..4e835a3f1ab4 100644
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -237,6 +237,10 @@ config CLK_RZV2H
> bool "RZ/V2H(P) family clock support" if COMPILE_TEST
> select RESET_CONTROLLER
>
> +config CLK_RENESAS_VBATTB
> + bool "Renesas VBATTB clock controller"
tristate
> + select RESET_CONTROLLER
> +
...
> +
> +static const struct of_device_id vbattb_clk_match[] = {
> + { .compatible = "renesas,r9a08g045-vbattb" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, vbattb_clk_match);
> +
> +static struct platform_driver vbattb_clk_driver = {
> + .driver = {
> + .name = "renesas-vbattb-clk",
> + .of_match_table = vbattb_clk_match,
> + },
> + .probe = vbattb_clk_probe,
> +};
> +module_platform_driver(vbattb_clk_driver);
That's a module, isn't it?
> +
> +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver");
> +MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
> +MODULE_LICENSE("GPL");
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver
2024-10-31 7:48 ` Krzysztof Kozlowski
@ 2024-10-31 8:43 ` Geert Uytterhoeven
2024-10-31 9:26 ` Claudiu Beznea
0 siblings, 1 reply; 23+ messages in thread
From: Geert Uytterhoeven @ 2024-10-31 8:43 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Claudiu, mturquette, sboyd, robh, krzk+dt, conor+dt,
alexandre.belloni, magnus.damm, p.zabel, linux-renesas-soc,
linux-clk, devicetree, linux-kernel, linux-rtc, linux-arm-kernel,
Claudiu Beznea
Hi Krzysztof,
On Thu, Oct 31, 2024 at 8:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Wed, Oct 30, 2024 at 01:01:13PM +0200, Claudiu wrote:
> > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
> > by the RTC. The input to the VBATTB could be a 32KHz crystal
> > or an external clock device.
> >
> > The HW block diagram for the clock generator is as follows:
> >
> > +----------+ XC `\
> > RTXIN --->| |----->| \ +----+ VBATTCLK
> > | 32K clock| | |----->|gate|----------->
> > | osc | XBYP | | +----+
> > RTXOUT --->| |----->| /
> > +----------+ ,
> >
> > After discussions w/ Stephen Boyd the clock tree associated with this
> > hardware block was exported in Linux as:
> >
> > vbattb-xtal
> > xbyp
> > xc
> > mux
> > vbattbclk
> >
> > where:
> > - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
> > - xc, xbyp are mux inputs
> > - mux is the internal mux
> > - vbattclk is the gate clock that feeds in the end the RTC
> >
> > to allow selecting the input of the MUX though assigned-clock DT
> > properties, using the already existing clock drivers and avoid adding
> > other DT properties. If the crystal is connected on RTXIN,
> > RTXOUT pins the XC will be selected as mux input. If an external clock
> > device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
> > mux input.
> >
> > The load capacitance of the internal crystal can be configured
> > with renesas,vbattb-load-nanofarads DT property.
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > --- a/drivers/clk/renesas/Kconfig
> > +++ b/drivers/clk/renesas/Kconfig
> > @@ -237,6 +237,10 @@ config CLK_RZV2H
> > bool "RZ/V2H(P) family clock support" if COMPILE_TEST
> > select RESET_CONTROLLER
> >
> > +config CLK_RENESAS_VBATTB
> > + bool "Renesas VBATTB clock controller"
>
> tristate
Good point.
However, does it work as a module, or would that break the RTC?
And this is missing
depends on ARCH_RENESAS || COMPILE_TEST
which I can add while applying.
>
> > + select RESET_CONTROLLER
> > +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver
2024-10-31 8:43 ` Geert Uytterhoeven
@ 2024-10-31 9:26 ` Claudiu Beznea
2024-10-31 9:46 ` Krzysztof Kozlowski
0 siblings, 1 reply; 23+ messages in thread
From: Claudiu Beznea @ 2024-10-31 9:26 UTC (permalink / raw)
To: Geert Uytterhoeven, Krzysztof Kozlowski
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, alexandre.belloni,
magnus.damm, p.zabel, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, linux-rtc, linux-arm-kernel, Claudiu Beznea
Hi, Geert, Krzysztof,
On 31.10.2024 10:43, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Thu, Oct 31, 2024 at 8:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On Wed, Oct 30, 2024 at 01:01:13PM +0200, Claudiu wrote:
>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>
>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
>>> by the RTC. The input to the VBATTB could be a 32KHz crystal
>>> or an external clock device.
>>>
>>> The HW block diagram for the clock generator is as follows:
>>>
>>> +----------+ XC `\
>>> RTXIN --->| |----->| \ +----+ VBATTCLK
>>> | 32K clock| | |----->|gate|----------->
>>> | osc | XBYP | | +----+
>>> RTXOUT --->| |----->| /
>>> +----------+ ,
>>>
>>> After discussions w/ Stephen Boyd the clock tree associated with this
>>> hardware block was exported in Linux as:
>>>
>>> vbattb-xtal
>>> xbyp
>>> xc
>>> mux
>>> vbattbclk
>>>
>>> where:
>>> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
>>> - xc, xbyp are mux inputs
>>> - mux is the internal mux
>>> - vbattclk is the gate clock that feeds in the end the RTC
>>>
>>> to allow selecting the input of the MUX though assigned-clock DT
>>> properties, using the already existing clock drivers and avoid adding
>>> other DT properties. If the crystal is connected on RTXIN,
>>> RTXOUT pins the XC will be selected as mux input. If an external clock
>>> device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
>>> mux input.
>>>
>>> The load capacitance of the internal crystal can be configured
>>> with renesas,vbattb-load-nanofarads DT property.
>>>
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
>>> --- a/drivers/clk/renesas/Kconfig
>>> +++ b/drivers/clk/renesas/Kconfig
>>> @@ -237,6 +237,10 @@ config CLK_RZV2H
>>> bool "RZ/V2H(P) family clock support" if COMPILE_TEST
>>> select RESET_CONTROLLER
>>>
>>> +config CLK_RENESAS_VBATTB
>>> + bool "Renesas VBATTB clock controller"
>>
>> tristate
>
> Good point.
> However, does it work as a module, or would that break the RTC?
On RZ/G3S the RTC counter needs the clock provided by VBATTB.
I'll try with this as a module.
>
> And this is missing
>
> depends on ARCH_RENESAS || COMPILE_TEST
>
> which I can add while applying.
Thank you!
Claudiu
>
>>
>>> + select RESET_CONTROLLER
>>> +
>
> Gr{oetje,eeting}s,
>
> Geert
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver
2024-10-31 9:26 ` Claudiu Beznea
@ 2024-10-31 9:46 ` Krzysztof Kozlowski
2024-11-01 8:53 ` Claudiu Beznea
0 siblings, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 9:46 UTC (permalink / raw)
To: Claudiu Beznea, Geert Uytterhoeven
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, alexandre.belloni,
magnus.damm, p.zabel, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, linux-rtc, linux-arm-kernel, Claudiu Beznea
On 31/10/2024 10:26, Claudiu Beznea wrote:
> Hi, Geert, Krzysztof,
>
> On 31.10.2024 10:43, Geert Uytterhoeven wrote:
>> Hi Krzysztof,
>>
>> On Thu, Oct 31, 2024 at 8:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>> On Wed, Oct 30, 2024 at 01:01:13PM +0200, Claudiu wrote:
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
>>>> by the RTC. The input to the VBATTB could be a 32KHz crystal
>>>> or an external clock device.
>>>>
>>>> The HW block diagram for the clock generator is as follows:
>>>>
>>>> +----------+ XC `\
>>>> RTXIN --->| |----->| \ +----+ VBATTCLK
>>>> | 32K clock| | |----->|gate|----------->
>>>> | osc | XBYP | | +----+
>>>> RTXOUT --->| |----->| /
>>>> +----------+ ,
>>>>
>>>> After discussions w/ Stephen Boyd the clock tree associated with this
>>>> hardware block was exported in Linux as:
>>>>
>>>> vbattb-xtal
>>>> xbyp
>>>> xc
>>>> mux
>>>> vbattbclk
>>>>
>>>> where:
>>>> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
>>>> - xc, xbyp are mux inputs
>>>> - mux is the internal mux
>>>> - vbattclk is the gate clock that feeds in the end the RTC
>>>>
>>>> to allow selecting the input of the MUX though assigned-clock DT
>>>> properties, using the already existing clock drivers and avoid adding
>>>> other DT properties. If the crystal is connected on RTXIN,
>>>> RTXOUT pins the XC will be selected as mux input. If an external clock
>>>> device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
>>>> mux input.
>>>>
>>>> The load capacitance of the internal crystal can be configured
>>>> with renesas,vbattb-load-nanofarads DT property.
>>>>
>>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>>>> --- a/drivers/clk/renesas/Kconfig
>>>> +++ b/drivers/clk/renesas/Kconfig
>>>> @@ -237,6 +237,10 @@ config CLK_RZV2H
>>>> bool "RZ/V2H(P) family clock support" if COMPILE_TEST
>>>> select RESET_CONTROLLER
>>>>
>>>> +config CLK_RENESAS_VBATTB
>>>> + bool "Renesas VBATTB clock controller"
>>>
>>> tristate
>>
>> Good point.
>> However, does it work as a module, or would that break the RTC?
>
> On RZ/G3S the RTC counter needs the clock provided by VBATTB.
>
> I'll try with this as a module.
So it will defer, why would this be a problem? This does not look like
critical core component, which would halt the system probe (and even
then systems like Android put everything as modules).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: (subset) [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
` (10 preceding siblings ...)
2024-10-30 15:50 ` [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Geert Uytterhoeven
@ 2024-10-31 23:17 ` Alexandre Belloni
11 siblings, 0 replies; 23+ messages in thread
From: Alexandre Belloni @ 2024-10-31 23:17 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm, p.zabel, Claudiu
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel, linux-rtc,
linux-arm-kernel, Claudiu Beznea
On Wed, 30 Oct 2024 13:01:10 +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Hi,
>
> On the Renesas RZ/G3S SoC the RTC clock is provided by the VBATTB
> IP. A 32 KHz crystall oscillator could be connected to the VBATTB
> input pins. The logic to control this clock (and pass it to RTC)
> is inside the VBATTB IP. For this, the clk-vbattb driver was added
> (patches 01-03/12).
>
> [...]
Applied, thanks!
[04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP
https://git.kernel.org/abelloni/c/71c61a45c951
[05/10] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC
https://git.kernel.org/abelloni/c/d4488377609e
Best regards,
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver
2024-10-31 9:46 ` Krzysztof Kozlowski
@ 2024-11-01 8:53 ` Claudiu Beznea
0 siblings, 0 replies; 23+ messages in thread
From: Claudiu Beznea @ 2024-11-01 8:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven
Cc: mturquette, sboyd, robh, krzk+dt, conor+dt, alexandre.belloni,
magnus.damm, p.zabel, linux-renesas-soc, linux-clk, devicetree,
linux-kernel, linux-rtc, linux-arm-kernel, Claudiu Beznea
On 31.10.2024 11:46, Krzysztof Kozlowski wrote:
> On 31/10/2024 10:26, Claudiu Beznea wrote:
>> Hi, Geert, Krzysztof,
>>
>> On 31.10.2024 10:43, Geert Uytterhoeven wrote:
>>> Hi Krzysztof,
>>>
>>> On Thu, Oct 31, 2024 at 8:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>> On Wed, Oct 30, 2024 at 01:01:13PM +0200, Claudiu wrote:
>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>
>>>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
>>>>> by the RTC. The input to the VBATTB could be a 32KHz crystal
>>>>> or an external clock device.
>>>>>
>>>>> The HW block diagram for the clock generator is as follows:
>>>>>
>>>>> +----------+ XC `\
>>>>> RTXIN --->| |----->| \ +----+ VBATTCLK
>>>>> | 32K clock| | |----->|gate|----------->
>>>>> | osc | XBYP | | +----+
>>>>> RTXOUT --->| |----->| /
>>>>> +----------+ ,
>>>>>
>>>>> After discussions w/ Stephen Boyd the clock tree associated with this
>>>>> hardware block was exported in Linux as:
>>>>>
>>>>> vbattb-xtal
>>>>> xbyp
>>>>> xc
>>>>> mux
>>>>> vbattbclk
>>>>>
>>>>> where:
>>>>> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
>>>>> - xc, xbyp are mux inputs
>>>>> - mux is the internal mux
>>>>> - vbattclk is the gate clock that feeds in the end the RTC
>>>>>
>>>>> to allow selecting the input of the MUX though assigned-clock DT
>>>>> properties, using the already existing clock drivers and avoid adding
>>>>> other DT properties. If the crystal is connected on RTXIN,
>>>>> RTXOUT pins the XC will be selected as mux input. If an external clock
>>>>> device is connected on RTXIN, RTXOUT pins the XBYP will be selected as
>>>>> mux input.
>>>>>
>>>>> The load capacitance of the internal crystal can be configured
>>>>> with renesas,vbattb-load-nanofarads DT property.
>>>>>
>>>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>
>>>>> --- a/drivers/clk/renesas/Kconfig
>>>>> +++ b/drivers/clk/renesas/Kconfig
>>>>> @@ -237,6 +237,10 @@ config CLK_RZV2H
>>>>> bool "RZ/V2H(P) family clock support" if COMPILE_TEST
>>>>> select RESET_CONTROLLER
>>>>>
>>>>> +config CLK_RENESAS_VBATTB
>>>>> + bool "Renesas VBATTB clock controller"
>>>>
>>>> tristate
>>>
>>> Good point.
>>> However, does it work as a module, or would that break the RTC?
>>
>> On RZ/G3S the RTC counter needs the clock provided by VBATTB.
>>
>> I'll try with this as a module.
>
> So it will defer, why would this be a problem? This does not look like
No problems with it. I wrongly phrased it. That being said, I'll set
CLK_RENESAS_VBATTB as module along with RTC and do the proper adjustments
in drivers/clk/renesas/Kconfig.
Thank you,
Claudiu
> critical core component, which would halt the system probe (and even
> then systems like Android put everything as modules).
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2024-11-01 8:53 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-30 11:01 [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Claudiu
2024-10-30 11:01 ` [PATCH v5 01/10] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Claudiu
2024-10-31 7:46 ` Krzysztof Kozlowski
2024-10-30 11:01 ` [PATCH v5 02/10] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Claudiu
2024-10-30 19:47 ` Stephen Boyd
2024-10-30 11:01 ` [PATCH v5 03/10] clk: renesas: clk-vbattb: Add VBATTB clock driver Claudiu
2024-10-31 7:48 ` Krzysztof Kozlowski
2024-10-31 8:43 ` Geert Uytterhoeven
2024-10-31 9:26 ` Claudiu Beznea
2024-10-31 9:46 ` Krzysztof Kozlowski
2024-11-01 8:53 ` Claudiu Beznea
2024-10-30 11:01 ` [PATCH v5 04/10] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Claudiu
2024-10-30 15:43 ` Geert Uytterhoeven
2024-10-30 11:01 ` [PATCH v5 05/10] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Claudiu
2024-10-30 11:01 ` [PATCH v5 06/10] arm64: dts: renesas: r9a08g045: Add VBATTB node Claudiu
2024-10-30 11:01 ` [PATCH v5 07/10] arm64: dts: renesas: r9a08g045: Add RTC node Claudiu
2024-10-30 11:01 ` [PATCH v5 08/10] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Claudiu
2024-10-30 11:01 ` [PATCH v5 09/10] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Claudiu
2024-10-30 11:01 ` [PATCH v5 10/10] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Claudiu
2024-10-31 7:47 ` Krzysztof Kozlowski
2024-10-30 15:50 ` [PATCH v5 00/10] Add RTC support for the Renesas RZ/G3S SoC Geert Uytterhoeven
2024-10-30 18:56 ` Alexandre Belloni
2024-10-31 23:17 ` (subset) " Alexandre Belloni
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