* [PATCH v2 0/3] rtc: rzn1: support XTAL clk and SCMP method
@ 2025-05-23 15:05 Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 1/3] dt-bindings: rtc: rzn1: add optional second clock Wolfram Sang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Wolfram Sang @ 2025-05-23 15:05 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Alexandre Belloni, Conor Dooley, devicetree,
Geert Uytterhoeven, Krzysztof Kozlowski, linux-rtc, Magnus Damm,
Miquel Raynal, Rob Herring
So far, the code and the binding for the RZ/N1D RTC assumed an input
clock of 32768Hz, so it was not explicitly described. It makes sense to
do this, though. For one reason, clocks with other frequencies might be
used. This RTC supports that via the SCMP counting method. The other
reason is, upcoming SoCs may have only the SCMP method described, so we
need to use it there later.
This series lets the driver handle the optional "xtal" clock and switch
to the SCMP method if suitable. It has been tested on a Renesas RZ/N1D
board with hacked devicetree values.
A branch with updated DTs can be found here:
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/n1d/enablement
Looking forward to comments!
Changes since v1:
- renamed variable from 'use_scmp' to 'scmp_val' to make clear it is not
a bool (patch 3)
- added tags from Geert (Thanks!)
- rebased to linux-next
Wolfram Sang (3):
dt-bindings: rtc: rzn1: add optional second clock
rtc: rzn1: Disable controller before initialization
rtc: rzn1: support input frequencies other than 32768Hz
.../bindings/rtc/renesas,rzn1-rtc.yaml | 8 ++-
drivers/rtc/rtc-rzn1.c | 59 +++++++++++++++----
2 files changed, 53 insertions(+), 14 deletions(-)
--
2.47.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] dt-bindings: rtc: rzn1: add optional second clock
2025-05-23 15:05 [PATCH v2 0/3] rtc: rzn1: support XTAL clk and SCMP method Wolfram Sang
@ 2025-05-23 15:05 ` Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 2/3] rtc: rzn1: Disable controller before initialization Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz Wolfram Sang
2 siblings, 0 replies; 6+ messages in thread
From: Wolfram Sang @ 2025-05-23 15:05 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Krzysztof Kozlowski, Geert Uytterhoeven,
Miquel Raynal, Alexandre Belloni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-rtc,
devicetree
The external crystal can be a second clock input. It is needed for the
SCMP counting method which allows using crystals different than 32768Hz.
It is also needed for an upcoming SoC which only supports the SCMP
method.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../devicetree/bindings/rtc/renesas,rzn1-rtc.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
index f6e0c613af67..f6fdcc7090b6 100644
--- a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
@@ -33,10 +33,14 @@ properties:
- const: pps
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clock-names:
- const: hclk
+ minItems: 1
+ items:
+ - const: hclk
+ - const: xtal
power-domains:
maxItems: 1
--
2.47.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] rtc: rzn1: Disable controller before initialization
2025-05-23 15:05 [PATCH v2 0/3] rtc: rzn1: support XTAL clk and SCMP method Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 1/3] dt-bindings: rtc: rzn1: add optional second clock Wolfram Sang
@ 2025-05-23 15:05 ` Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz Wolfram Sang
2 siblings, 0 replies; 6+ messages in thread
From: Wolfram Sang @ 2025-05-23 15:05 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Miquel Raynal, Alexandre Belloni, linux-rtc
Datasheet says that the controller must be disabled before setting up
either SUBU or SCMP. This did not matter so far because the driver only
supported SUBU which was the default, too. It is good practice to follow
datasheet recommendations, though. It will also be needed because SCMP
mode will be added in a later patch.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/rtc/rtc-rzn1.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
index 3c2861983ff1..7777df1e3426 100644
--- a/drivers/rtc/rtc-rzn1.c
+++ b/drivers/rtc/rtc-rzn1.c
@@ -25,6 +25,7 @@
#define RZN1_RTC_CTL0_SLSB_SUBU 0
#define RZN1_RTC_CTL0_SLSB_SCMP BIT(4)
#define RZN1_RTC_CTL0_AMPM BIT(5)
+#define RZN1_RTC_CTL0_CEST BIT(6)
#define RZN1_RTC_CTL0_CE BIT(7)
#define RZN1_RTC_CTL1 0x04
@@ -369,6 +370,7 @@ static const struct rtc_class_ops rzn1_rtc_ops = {
static int rzn1_rtc_probe(struct platform_device *pdev)
{
struct rzn1_rtc *rtc;
+ u32 val;
int irq;
int ret;
@@ -406,6 +408,14 @@ static int rzn1_rtc_probe(struct platform_device *pdev)
* Ensure the clock counter is enabled.
* Set 24-hour mode and possible oscillator offset compensation in SUBU mode.
*/
+ val = readl(rtc->base + RZN1_RTC_CTL0) & ~RZN1_RTC_CTL0_CE;
+ writel(val, rtc->base + RZN1_RTC_CTL0);
+ /* Wait 2-4 32k clock cycles for the disabled controller */
+ ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL0, val,
+ !(val & RZN1_RTC_CTL0_CEST), 62, 123);
+ if (ret)
+ goto dis_runtime_pm;
+
writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
rtc->base + RZN1_RTC_CTL0);
--
2.47.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz
2025-05-23 15:05 [PATCH v2 0/3] rtc: rzn1: support XTAL clk and SCMP method Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 1/3] dt-bindings: rtc: rzn1: add optional second clock Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 2/3] rtc: rzn1: Disable controller before initialization Wolfram Sang
@ 2025-05-23 15:05 ` Wolfram Sang
2025-05-26 7:22 ` Miquel Raynal
2 siblings, 1 reply; 6+ messages in thread
From: Wolfram Sang @ 2025-05-23 15:05 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Geert Uytterhoeven, Miquel Raynal,
Alexandre Belloni, linux-rtc
When using the SCMP mode instead of SUBU, this RTC can also support
other input frequencies than 32768Hz. Also, upcoming SoCs will only
support SCMP.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/rtc/rtc-rzn1.c | 51 +++++++++++++++++++++++++++++++-----------
1 file changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
index 7777df1e3426..33fd20f37588 100644
--- a/drivers/rtc/rtc-rzn1.c
+++ b/drivers/rtc/rtc-rzn1.c
@@ -12,6 +12,7 @@
*/
#include <linux/bcd.h>
+#include <linux/clk.h>
#include <linux/init.h>
#include <linux/iopoll.h>
#include <linux/module.h>
@@ -22,7 +23,6 @@
#include <linux/spinlock.h>
#define RZN1_RTC_CTL0 0x00
-#define RZN1_RTC_CTL0_SLSB_SUBU 0
#define RZN1_RTC_CTL0_SLSB_SCMP BIT(4)
#define RZN1_RTC_CTL0_AMPM BIT(5)
#define RZN1_RTC_CTL0_CEST BIT(6)
@@ -50,6 +50,8 @@
#define RZN1_RTC_SUBU_DEV BIT(7)
#define RZN1_RTC_SUBU_DECR BIT(6)
+#define RZN1_RTC_SCMP 0x3c
+
#define RZN1_RTC_ALM 0x40
#define RZN1_RTC_ALH 0x44
#define RZN1_RTC_ALW 0x48
@@ -357,22 +359,21 @@ static int rzn1_rtc_set_offset(struct device *dev, long offset)
return 0;
}
-static const struct rtc_class_ops rzn1_rtc_ops = {
+static struct rtc_class_ops rzn1_rtc_ops = {
.read_time = rzn1_rtc_read_time,
.set_time = rzn1_rtc_set_time,
.read_alarm = rzn1_rtc_read_alarm,
.set_alarm = rzn1_rtc_set_alarm,
.alarm_irq_enable = rzn1_rtc_alarm_irq_enable,
- .read_offset = rzn1_rtc_read_offset,
- .set_offset = rzn1_rtc_set_offset,
};
static int rzn1_rtc_probe(struct platform_device *pdev)
{
struct rzn1_rtc *rtc;
- u32 val;
- int irq;
- int ret;
+ u32 val, scmp_val = 0;
+ struct clk *xtal;
+ unsigned long rate;
+ int irq, ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
@@ -404,10 +405,24 @@ static int rzn1_rtc_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- /*
- * Ensure the clock counter is enabled.
- * Set 24-hour mode and possible oscillator offset compensation in SUBU mode.
- */
+ /* Only switch to scmp if we have an xtal clock with a valid rate and != 32768 */
+ xtal = devm_clk_get_optional(&pdev->dev, "xtal");
+ if (IS_ERR(xtal)) {
+ ret = PTR_ERR(xtal);
+ goto dis_runtime_pm;
+ } else if (xtal) {
+ rate = clk_get_rate(xtal);
+
+ if (rate < 32000 || rate > BIT(22)) {
+ ret = -EOPNOTSUPP;
+ goto dis_runtime_pm;
+ }
+
+ if (rate != 32768)
+ scmp_val = RZN1_RTC_CTL0_SLSB_SCMP;
+ }
+
+ /* Disable controller during SUBU/SCMP setup */
val = readl(rtc->base + RZN1_RTC_CTL0) & ~RZN1_RTC_CTL0_CE;
writel(val, rtc->base + RZN1_RTC_CTL0);
/* Wait 2-4 32k clock cycles for the disabled controller */
@@ -416,8 +431,18 @@ static int rzn1_rtc_probe(struct platform_device *pdev)
if (ret)
goto dis_runtime_pm;
- writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
- rtc->base + RZN1_RTC_CTL0);
+ /* Set desired modes while leaving the controller disabled */
+ writel(RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0);
+
+ if (scmp_val) {
+ writel(rate - 1, rtc->base + RZN1_RTC_SCMP);
+ } else {
+ rzn1_rtc_ops.read_offset = rzn1_rtc_read_offset;
+ rzn1_rtc_ops.set_offset = rzn1_rtc_set_offset;
+ }
+
+ /* Enable controller finally */
+ writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0);
/* Disable all interrupts */
writel(0, rtc->base + RZN1_RTC_CTL1);
--
2.47.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz
2025-05-23 15:05 ` [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz Wolfram Sang
@ 2025-05-26 7:22 ` Miquel Raynal
2025-05-26 7:38 ` Wolfram Sang
0 siblings, 1 reply; 6+ messages in thread
From: Miquel Raynal @ 2025-05-26 7:22 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Geert Uytterhoeven, Alexandre Belloni,
linux-rtc
Hello Wolfram,
...
> @@ -357,22 +359,21 @@ static int rzn1_rtc_set_offset(struct device *dev, long offset)
> return 0;
> }
>
> -static const struct rtc_class_ops rzn1_rtc_ops = {
> +static struct rtc_class_ops rzn1_rtc_ops = {
> .read_time = rzn1_rtc_read_time,
> .set_time = rzn1_rtc_set_time,
> .read_alarm = rzn1_rtc_read_alarm,
> .set_alarm = rzn1_rtc_set_alarm,
> .alarm_irq_enable = rzn1_rtc_alarm_irq_enable,
> - .read_offset = rzn1_rtc_read_offset,
> - .set_offset = rzn1_rtc_set_offset,
> };
...
> - writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
> - rtc->base + RZN1_RTC_CTL0);
> + /* Set desired modes while leaving the controller disabled */
> + writel(RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0);
> +
> + if (scmp_val) {
> + writel(rate - 1, rtc->base + RZN1_RTC_SCMP);
> + } else {
> + rzn1_rtc_ops.read_offset = rzn1_rtc_read_offset;
> + rzn1_rtc_ops.set_offset = rzn1_rtc_set_offset;
I guess this situation is not possible but let me ask. Do we care
about the very unlikely case where two RTCs are available and configured
differently? Because we are overwriting a static entry here. Maybe we
could have two static structures and pick the correct one during probe
instead.
> + }
> +
> + /* Enable controller finally */
> + writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0);
>
> /* Disable all interrupts */
> writel(0, rtc->base + RZN1_RTC_CTL1);
Anyhow, I don't see this comment as a no-go so,
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz
2025-05-26 7:22 ` Miquel Raynal
@ 2025-05-26 7:38 ` Wolfram Sang
0 siblings, 0 replies; 6+ messages in thread
From: Wolfram Sang @ 2025-05-26 7:38 UTC (permalink / raw)
To: Miquel Raynal
Cc: linux-renesas-soc, Geert Uytterhoeven, Alexandre Belloni,
linux-rtc
[-- Attachment #1: Type: text/plain, Size: 524 bytes --]
> > + rzn1_rtc_ops.read_offset = rzn1_rtc_read_offset;
> > + rzn1_rtc_ops.set_offset = rzn1_rtc_set_offset;
>
> I guess this situation is not possible but let me ask. Do we care
> about the very unlikely case where two RTCs are available and configured
> differently? Because we are overwriting a static entry here. Maybe we
> could have two static structures and pick the correct one during probe
> instead.
True, it is so highly unlikely that I didn't think of it. But
theoretically possible, I'll fix.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2025-05-23 15:05 [PATCH v2 0/3] rtc: rzn1: support XTAL clk and SCMP method Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 1/3] dt-bindings: rtc: rzn1: add optional second clock Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 2/3] rtc: rzn1: Disable controller before initialization Wolfram Sang
2025-05-23 15:05 ` [PATCH v2 3/3] rtc: rzn1: support input frequencies other than 32768Hz Wolfram Sang
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2025-05-26 7:38 ` Wolfram Sang
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