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([49.204.165.28]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85770b9e2esm7565285a12.0.2026.05.31.10.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 May 2026 10:11:08 -0700 (PDT) From: Udaya Kiran Challa To: alchark@gmail.com, krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, me@brighamcampbell.com, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Udaya Kiran Challa Subject: [PATCH v5] dt-bindings: clock: via,vt8500: Convert to DT Schema Date: Sun, 31 May 2026 22:39:55 +0530 Message-ID: <20260531171041.4149-1-challauday369@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-rtc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert the VIA/Wondermedia VT8500 and Wondermedia WM8xxx series SoCs clock controller binding from the legacy text format to DT schema. Signed-off-by: Udaya Kiran Challa --- Changelog: Changes since v4: - Remove schema select matching for via,vt8500-pmc - Add dependentRequired validation for divisor-mask - Fix maintainers list - Add reg false condition for device clock - Fix example validation against clocks child node Link to v4:https://lore.kernel.org/all/20260524151110.21277-1-challauday369@gmail.com/ Changes since v3: - Add schema select matching for via,vt8500-pmc - Allow hyphen in node names under patternProperties - Add dependentRequired validation for enable-reg/enable-bit - Fix example validation against PMC schema Link to v3:https://lore.kernel.org/all/20260524111813.39810-1-challauday369@gmail.com/ Changes since v2: - Drop redundant description for clocks - Disable reg property for device clocks - Fix schema hierarchy to match actual DTS structure Link to v2:https://lore.kernel.org/all/20260521170810.19702-1-challauday369@gmail.com/ Changes since v1: - Add default value for divisor-mask - Add required properties compatible and model - Fix example node name - Update example size cells and reg value Link to v1:https://lore.kernel.org/all/20260520025131.17772-1-challauday369@gmail.com/ --- .../bindings/clock/via,vt8500-clock.yaml | 133 ++++++++++++++++++ .../devicetree/bindings/clock/vt8500.txt | 74 ---------- 2 files changed, 133 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml delete mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt diff --git a/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml new file mode 100644 index 000000000000..e2e674d95654 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/via,vt8500-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Clock Controller + +maintainers: + - Alexey Charkov + - Krzysztof Kozlowski + +description: + Clock controller bindings for VIA/Wondermedia VT8500 and Wondermedia WM8xxx + series SoCs. + +properties: + compatible: + enum: + - via,vt8500-pll-clock + - wm,wm8650-pll-clock + - wm,wm8750-pll-clock + - wm,wm8850-pll-clock + - via,vt8500-device-clock + + reg: + description: Offset of the PLL register within the PMC register space. + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + enable-reg: + description: Offset of the clock enable register within the PMC register space. + $ref: /schemas/types.yaml#/definitions/uint32 + + enable-bit: + description: Bit index controlling clock enable. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + + divisor-reg: + description: Offset of the clock divisor register within the PMC register space. + $ref: /schemas/types.yaml#/definitions/uint32 + + divisor-mask: + description: Bitmask describing the divisor field inside divisor-reg. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x1f + +required: + - compatible + - clocks + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + const: via,vt8500-device-clock + then: + properties: + reg: false + anyOf: + - required: + - enable-reg + - enable-bit + - required: + - divisor-reg + - if: + properties: + compatible: + enum: + - via,vt8500-pll-clock + - wm,wm8650-pll-clock + - wm,wm8750-pll-clock + - wm,wm8850-pll-clock + then: + required: + - reg + +dependentRequired: + enable-reg: + - enable-bit + enable-bit: + - enable-reg + divisor-mask: + - divisor-reg + +additionalProperties: false + +examples: + - | + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref25: clock-25000000 { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + + plla: clock@200 { + compatible = "wm,wm8650-pll-clock"; + reg = <0x200>; + clocks = <&ref25>; + #clock-cells = <0>; + }; + + pllb: clock@204 { + compatible = "wm,wm8650-pll-clock"; + reg = <0x204>; + clocks = <&ref25>; + #clock-cells = <0>; + }; + + clksdhc: sdhc { + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + #clock-cells = <0>; + divisor-reg = <0x328>; + divisor-mask = <0x3f>; + enable-reg = <0x254>; + enable-bit = <18>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt deleted file mode 100644 index 91d71cc0314a..000000000000 --- a/Documentation/devicetree/bindings/clock/vt8500.txt +++ /dev/null @@ -1,74 +0,0 @@ -Device Tree Clock bindings for arch-vt8500 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock - "wm,wm8650-pll-clock" - for a WM8650 PLL clock - "wm,wm8750-pll-clock" - for a WM8750 PLL clock - "wm,wm8850-pll-clock" - for a WM8850 PLL clock - "via,vt8500-device-clock" - for a VT/WM device clock - -Required properties for PLL clocks: -- reg : shall be the control register offset from PMC base for the pll clock. -- clocks : shall be the input parent clock phandle for the clock. This should - be the reference clock. -- #clock-cells : from common clock binding; shall be set to 0. - -Required properties for device clocks: -- clocks : shall be the input parent clock phandle for the clock. This should - be a pll output. -- #clock-cells : from common clock binding; shall be set to 0. - - -Device Clocks - -Device clocks are required to have one or both of the following sets of -properties: - - -Gated device clocks: - -Required properties: -- enable-reg : shall be the register offset from PMC base for the enable - register. -- enable-bit : shall be the bit within enable-reg to enable/disable the clock. - - -Divisor device clocks: - -Required property: -- divisor-reg : shall be the register offset from PMC base for the divisor - register. -Optional property: -- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f - if not specified. - - -For example: - -ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; -}; - -plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; -}; - -sdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; -}; -- 2.43.0