* Re: [PATCH v6 2/2] rtc: Add NXP PCF85053 driver support
From: kernel test robot @ 2025-11-18 20:58 UTC (permalink / raw)
To: Lakshay Piplani, alexandre.belloni, linux-rtc, linux-kernel, robh,
krzk+dt, conor+dt, devicetree
Cc: oe-kbuild-all, pankit.garg, vikash.bansal, priyanka.jain,
shashank.rebbapragada, Lakshay Piplani, Daniel Aguirre
In-Reply-To: <20251113054243.4045820-2-lakshay.piplani@nxp.com>
Hi Lakshay,
kernel test robot noticed the following build errors:
[auto build test ERROR on abelloni/rtc-next]
[also build test ERROR on linus/master v6.18-rc6 next-20251118]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Lakshay-Piplani/rtc-Add-NXP-PCF85053-driver-support/20251113-134432
base: https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-next
patch link: https://lore.kernel.org/r/20251113054243.4045820-2-lakshay.piplani%40nxp.com
patch subject: [PATCH v6 2/2] rtc: Add NXP PCF85053 driver support
config: sparc64-randconfig-001-20251119 (https://download.01.org/0day-ci/archive/20251119/202511190432.xfs91BVq-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251119/202511190432.xfs91BVq-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511190432.xfs91BVq-lkp@intel.com/
All error/warnings (new ones prefixed by >>):
drivers/rtc/rtc-pcf85053.c: In function 'pcf85053_probe':
>> drivers/rtc/rtc-pcf85053.c:616:14: error: implicit declaration of function 'i2c_check_functionality' [-Wimplicit-function-declaration]
616 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/rtc/rtc-pcf85053.c: At top level:
>> drivers/rtc/rtc-pcf85053.c:729:1: warning: data definition has no type or storage class
729 | module_i2c_driver(pcf85053_driver);
| ^~~~~~~~~~~~~~~~~
>> drivers/rtc/rtc-pcf85053.c:729:1: error: type defaults to 'int' in declaration of 'module_i2c_driver' [-Wimplicit-int]
>> drivers/rtc/rtc-pcf85053.c:729:1: error: parameter names (without types) in function declaration [-Wdeclaration-missing-parameter-type]
>> drivers/rtc/rtc-pcf85053.c:720:26: warning: 'pcf85053_driver' defined but not used [-Wunused-variable]
720 | static struct i2c_driver pcf85053_driver = {
| ^~~~~~~~~~~~~~~
vim +/i2c_check_functionality +616 drivers/rtc/rtc-pcf85053.c
608
609 static int pcf85053_probe(struct i2c_client *client)
610 {
611 struct pcf85053 *pcf85053;
612 const struct pcf85053_config *config;
613 const char *iface = NULL;
614 int err;
615
> 616 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
617 I2C_FUNC_SMBUS_BYTE |
618 I2C_FUNC_SMBUS_BLOCK_DATA))
619 return -ENODEV;
620
621 pcf85053 = devm_kzalloc(&client->dev, sizeof(struct pcf85053),
622 GFP_KERNEL);
623 if (!pcf85053)
624 return -ENOMEM;
625
626 config = i2c_get_match_data(client);
627 if (!config)
628 return -ENODEV;
629
630 pcf85053->regmap = devm_regmap_init_i2c(client, &config->regmap);
631 if (IS_ERR(pcf85053->regmap))
632 return PTR_ERR(pcf85053->regmap);
633
634 i2c_set_clientdata(client, pcf85053);
635
636 pcf85053->client = client;
637 device_set_wakeup_capable(&client->dev, 1);
638
639 pcf85053->is_primary = true;
640
641 if (of_property_read_string(client->dev.of_node, "nxp,interface", &iface))
642 return dev_err_probe(&client->dev, -EINVAL,
643 "Missing mandatory property: nxp,interface\n");
644 if (!strcmp(iface, "primary"))
645 pcf85053->is_primary = true;
646 else if (!strcmp(iface, "secondary"))
647 pcf85053->is_primary = false;
648 else
649 return dev_err_probe(&client->dev, -EINVAL,
650 "Invalid value for nxp,interface: %s\n", iface);
651
652 if (pcf85053->is_primary) {
653 unsigned int ctrl;
654 int err;
655
656 err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
657 if (err)
658 return err;
659
660 if (of_property_read_bool(client->dev.of_node, "nxp,write-access")) {
661 if (!(ctrl & PCF85053_BIT_TWO)) {
662 err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_CTRL,
663 PCF85053_BIT_TWO, PCF85053_BIT_TWO);
664 if (err)
665 return err;
666 }
667 dev_dbg(&client->dev, "Ownership set: TWO=1 (primary writes)\n");
668 } else {
669 /* TWO (Time Write Ownership) bit defaults to 0 (Secondary) */
670 dev_dbg(&client->dev, "Default ownership set: TWO=0 (secondary writes)\n");
671 }
672 }
673
674 pcf85053->rtc = devm_rtc_allocate_device(&client->dev);
675 if (IS_ERR(pcf85053->rtc))
676 return PTR_ERR(pcf85053->rtc);
677
678 pcf85053->rtc->ops = &pcf85053_rtc_ops;
679 pcf85053->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
680 pcf85053->rtc->range_max = RTC_TIMESTAMP_END_2099;
681 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85053->rtc->features);
682 clear_bit(RTC_FEATURE_ALARM, pcf85053->rtc->features);
683
684 if (config->has_alarms && client->irq > 0) {
685 err = devm_request_threaded_irq(&client->dev, client->irq,
686 NULL, pcf85053_irq,
687 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
688 "pcf85053", client);
689 if (err) {
690 dev_err(&client->dev, "unable to request IRQ %d\n", client->irq);
691 } else {
692 set_bit(RTC_FEATURE_ALARM, pcf85053->rtc->features);
693 device_init_wakeup(&client->dev, true);
694 err = dev_pm_set_wake_irq(&client->dev, client->irq);
695 if (err)
696 dev_err(&client->dev, "failed to enable irq wake\n");
697 }
698 }
699
700 #ifdef CONFIG_COMMON_CLK
701 /* register clk in common clk framework */
702 pcf85053_clkout_register_clk(pcf85053);
703 #endif
704
705 return devm_rtc_register_device(pcf85053->rtc);
706 }
707
708 static const struct i2c_device_id pcf85053_id[] = {
709 { "pcf85053", .driver_data = (kernel_ulong_t)&config_pcf85053 },
710 { }
711 };
712 MODULE_DEVICE_TABLE(i2c, pcf85053_id);
713
714 static const struct of_device_id pcf85053_of_match[] = {
715 { .compatible = "nxp,pcf85053", .data = &config_pcf85053 },
716 {}
717 };
718 MODULE_DEVICE_TABLE(of, pcf85053_of_match);
719
> 720 static struct i2c_driver pcf85053_driver = {
721 .driver = {
722 .name = "rtc-pcf85053",
723 .of_match_table = of_match_ptr(pcf85053_of_match),
724 },
725 .probe = pcf85053_probe,
726 .id_table = pcf85053_id,
727 };
728
> 729 module_i2c_driver(pcf85053_driver);
730
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v4 05/16] dt-bindings: mfd: ROHM BD72720
From: Linus Walleij @ 2025-11-18 23:06 UTC (permalink / raw)
To: Matti Vaittinen
Cc: Matti Vaittinen, Lee Jones, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sebastian Reichel,
Liam Girdwood, Mark Brown, Michael Turquette, Stephen Boyd,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <ec2cb44d9d00f5edaed2fbe17fd9ddbed914ff37.1763022807.git.mazziesaccount@gmail.com>
On Thu, Nov 13, 2025 at 9:52 AM Matti Vaittinen
<matti.vaittinen@linux.dev> wrote:
> From: Matti Vaittinen <mazziesaccount@gmail.com>
>
> The ROHM BD72720 is a power management IC integrating regulators, GPIOs,
> charger, LEDs, RTC and a clock gate.
>
> Add dt-binding doc for ROHM BD72720.
>
> Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
This is looking good!
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH next] rtc: atcrtc100: Fix signedness bug in probe()
From: CL Wang @ 2025-11-19 2:35 UTC (permalink / raw)
To: Dan Carpenter
Cc: Alexandre Belloni, linux-rtc, linux-kernel, kernel-janitors,
cl634
In-Reply-To: <aRxPGBEX8hbY6sjV@stanley.mountain>
On Tue, Nov 18, 2025 at 01:48:56PM +0300, Dan Carpenter wrote:
Hi Dan,
Thank you for pointing out the issue and for providing the fix.
You're absolutely correct that using an unsigned type for alarm_irq
prevents proper error handling when platform_get_irq() returns a
negative value. I will apply your patch and also review other return
value checks to ensure there are no similar issues elsewhere.
Thank you again for your detailed review and suggestions.
Best regards,
CL
>
> The "atcrtc_dev->alarm_irq" variable is an unsigned int but it needs to
> be signed for the error handling to work. Use the "ret" variable
> instead.
>
> Fixes: 7adca706fe16 ("rtc: atcrtc100: Add ATCRTC100 RTC driver")
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> drivers/rtc/rtc-atcrtc100.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/rtc/rtc-atcrtc100.c b/drivers/rtc/rtc-atcrtc100.c
> index 51933ae1a2fa..9808fc2c5a49 100644
> --- a/drivers/rtc/rtc-atcrtc100.c
> +++ b/drivers/rtc/rtc-atcrtc100.c
> @@ -296,10 +296,12 @@ static int atcrtc_probe(struct platform_device *pdev)
> "Failed to initialize RTC: unsupported hardware ID 0x%x\n",
> rtc_id);
>
> - atcrtc_dev->alarm_irq = platform_get_irq(pdev, 1);
> - if (atcrtc_dev->alarm_irq < 0)
> - return dev_err_probe(&pdev->dev, atcrtc_dev->alarm_irq,
> + ret = platform_get_irq(pdev, 1);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret,
> "Failed to get IRQ for alarm\n");
> + atcrtc_dev->alarm_irq = ret;
> +
> ret = devm_request_irq(&pdev->dev,
> atcrtc_dev->alarm_irq,
> atcrtc_alarm_isr,
> --
> 2.51.0
>
^ permalink raw reply
* Re: [PATCH next] rtc: atcrtc100: Fix signedness bug in probe()
From: Dan Carpenter @ 2025-11-19 7:13 UTC (permalink / raw)
To: CL Wang; +Cc: Alexandre Belloni, linux-rtc, linux-kernel, kernel-janitors
In-Reply-To: <aR0s653C4g2auavf@swlinux02>
On Wed, Nov 19, 2025 at 10:35:23AM +0800, CL Wang wrote:
> On Tue, Nov 18, 2025 at 01:48:56PM +0300, Dan Carpenter wrote:
>
> Hi Dan,
>
> Thank you for pointing out the issue and for providing the fix.
>
> You're absolutely correct that using an unsigned type for alarm_irq
> prevents proper error handling when platform_get_irq() returns a
> negative value. I will apply your patch and also review other return
> value checks to ensure there are no similar issues elsewhere.
>
> Thank you again for your detailed review and suggestions.
>
You're welcome. These are just Smatch warnings. Nothing super
major.
https://github.com/error27/smatch
https://github.com/error27/smatch/blob/master/Documentation/smatch.rst
regards,
dan carpenter
^ permalink raw reply
* [PATCH v3 1/5] dt-bindings: rtc: nxp,pcf85363: add timestamp mode config
From: Lakshay Piplani @ 2025-11-19 8:33 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree, wim, linux, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani
NXP PCF85263/PCF85363 provides three timestamp registers (TSR1-TSR3)
which latch the current time when a selected event occurs. Add a
vendor specific property, nxp,timestamp-mode, to select the event
source for each register.
Also introduce a new header 'pcf85363-tsr.h' to expose
macros for timestamp mode fields, improving readability
of device tree file.
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
---
V2 -> V3:
- No changes in v3
- Added Reviewed-by: Rob Herring <robh@kernel.org>
V1 -> V2:
- Addressed review comments from Rob Herring:
* use $ref: /schemas/types.yaml#/definitions/uint32-array
* tuple form with exactly 3 items (TSR1/TSR2/TSR3), per items decimal enums
* define 'nxp,timestamp-mode' clearly
* drop watchdog related vendor properties
* remove watchdog related vendor properties from i2c example
.../devicetree/bindings/rtc/nxp,pcf85363.yaml | 23 ++++++++++++++-
include/dt-bindings/rtc/pcf85363-tsr.h | 28 +++++++++++++++++++
2 files changed, 50 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/rtc/pcf85363-tsr.h
diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml
index 52aa3e2091e9..cf9c155162d6 100644
--- a/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/rtc/nxp,pcf85363.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Philips PCF85263/PCF85363 Real Time Clock
+title: NXP PCF85263/PCF85363 Real Time Clock
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
@@ -39,6 +39,24 @@ properties:
start-year: true
wakeup-source: true
+ nxp,timestamp-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - enum: [0, 1, 2] # TSR1: NONE, FE, LE
+ description: TSR1 mode
+ - enum: [0, 1, 2, 3, 4, 5] # TSR2: NONE, FB, LB, LV, FE, LE
+ description: TSR2 mode
+ - enum: [0, 1, 2, 3] # TSR3: NONE, FB, LB, LV
+ description: TSR3 mode
+ description: |
+ Defines timestamp modes for TSR1, TSR2, and TSR3.
+ Use macros from <dt-bindings/rtc/pcf85363-tsr.h>.
+
+ Each value corresponds to a mode constant:
+ - TSR1: NONE, FE, LE
+ - TSR2: NONE, FB, LB, LV, FE, LE
+ - TSR3: NONE, FB, LB, LV
+
required:
- compatible
- reg
@@ -47,6 +65,7 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/rtc/pcf85363-tsr.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -56,5 +75,7 @@ examples:
reg = <0x51>;
#clock-cells = <0>;
quartz-load-femtofarads = <12500>;
+ wakeup-source;
+ nxp,timestamp-mode = <PCF85363_TSR1_FE PCF85363_TSR2_LB PCF85363_TSR3_LV>;
};
};
diff --git a/include/dt-bindings/rtc/pcf85363-tsr.h b/include/dt-bindings/rtc/pcf85363-tsr.h
new file mode 100644
index 000000000000..1fb5b9b3601e
--- /dev/null
+++ b/include/dt-bindings/rtc/pcf85363-tsr.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef _DT_BINDINGS_RTC_PCF85363_TSR_H
+#define _DT_BINDINGS_RTC_PCF85363_TSR_H
+
+/* TSR1 modes */
+#define PCF85363_TSR1_NONE 0x00
+#define PCF85363_TSR1_FE 0x01
+#define PCF85363_TSR1_LE 0x02
+
+/* TSR2 modes */
+#define PCF85363_TSR2_NONE 0x00
+#define PCF85363_TSR2_FB 0x01
+#define PCF85363_TSR2_LB 0x02
+#define PCF85363_TSR2_LV 0x03
+#define PCF85363_TSR2_FE 0x04
+#define PCF85363_TSR2_LE 0x05
+
+/* TSR3 modes */
+#define PCF85363_TSR3_NONE 0x00
+#define PCF85363_TSR3_FB 0x01
+#define PCF85363_TSR3_LB 0x02
+#define PCF85363_TSR3_LV 0x03
+
+#endif /* _DT_BINDINGS_RTC_PCF85363_TSR_H */
--
2.25.1
^ permalink raw reply related
* [PATCH v3 5/5] rtc: pcf85363: add watchdog support with configurable step size
From: Lakshay Piplani @ 2025-11-19 8:33 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree, wim, linux, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani
In-Reply-To: <20251119083336.2241142-1-lakshay.piplani@nxp.com>
Add watchdog timer support to PCF85263/PCF85363 using the linux watchdog
subsystem. The driver programs the hardware watchdog timeout based on
the requested period.
Also use rtc_add_group() instead of sysfs_create_group() to register
timestamp attributes under the RTC class device (/sys/class/rtc/rtcX).
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
---
V2 -> V3:
- Split into separate patches as suggested:
- Battery switch-over detection.
- Timestamp recording for TS pin and battery switch-over events.
- Offset calibration.
- Watchdog timer (to be reviewed by watchdog maintainers).
- Dropped Alarm2 support
- Switched to rtc_add_group() for sysfs attributes
- Removed failure paths after RTC device registration as per subsystem guidelines.
V1 -> V2:
- Watchdog related changes due to removal of vendor specific properties
from device tree
* remove vendor DT knobs (enable/timeout/stepsize/repeat)
* use watchdog_init_timeout (with 10s default)
* derive clock_sel from final timeout
* default, repeat=true (repeat mode)
- Fixed uninitalised warning on 'ret' (reported by kernel test robot)
- Use dev_dbg instead of dev_info for debug related print messages
- Minor cleanup and comments
drivers/rtc/rtc-pcf85363.c | 168 +++++++++++++++++++++++++++++++++++--
1 file changed, 160 insertions(+), 8 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index 3d733375187b..34d4c2e16774 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -5,6 +5,10 @@
* Driver for NXP PCF85363 real-time clock.
*
* Copyright (C) 2017 Eric Nelson
+ *
+ * Copyright 2025 NXP
+ * Added support for timestamps, battery switch-over,
+ * watchdog, offset calibration.
*/
#include <linux/module.h>
#include <linux/i2c.h>
@@ -17,6 +21,8 @@
#include <linux/device.h>
#include <linux/of.h>
#include <linux/regmap.h>
+#include <linux/rtc.h>
+#include <linux/watchdog.h>
/*
* Date/Time registers
@@ -127,6 +133,18 @@
#define OFFSET_MAXIMUM 127
#define OFFSET_MASK 0xFF
+#define WD_MODE_REPEAT BIT(7)
+#define WD_TIMEOUT_MASK GENMASK(6, 2)
+#define WD_TIMEOUT_SHIFT 2
+#define WD_CLKSEL_MASK GENMASK(1, 0)
+#define WD_CLKSEL_0_25HZ 0x00
+#define WD_CLKSEL_1HZ 0x01
+#define WD_CLKSEL_4HZ 0x02
+#define WD_CLKSEL_16HZ 0x03
+
+#define WD_TIMEOUT_MIN 1
+#define WD_TIMEOUT_MAX 0x1F
+
struct pcf85363 {
struct rtc_device *rtc;
struct regmap *regmap;
@@ -138,6 +156,15 @@ struct pcf85x63_config {
unsigned int num_nvram;
};
+struct pcf85363_watchdog {
+ struct watchdog_device wdd;
+ struct regmap *regmap;
+ struct device *dev;
+ u8 timeout_val;
+ u8 clock_sel;
+ bool repeat;
+};
+
static int pcf85363_load_capacitance(struct pcf85363 *pcf85363, struct device_node *node)
{
u32 load = 7000;
@@ -323,12 +350,13 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
return IRQ_NONE;
if (flags) {
- dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s%s%s%s\n",
+ dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s%s%s%s%s\n",
flags, (flags & FLAGS_A1F) ? " [A1F]" : "",
(flags & FLAGS_TSR1F) ? " [TSR1F]" : "",
(flags & FLAGS_TSR2F) ? " [TSR2F]" : "",
(flags & FLAGS_TSR3F) ? " [TSR3F]" : "",
- (flags & FLAGS_BSF) ? " [BSF]" : "");
+ (flags & FLAGS_BSF) ? " [BSF]" : "",
+ (flags & FLAGS_WDF) ? " [WDF]" : "");
}
if (flags & FLAGS_A1F) {
@@ -360,6 +388,11 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
handled = true;
}
+ if (flags & FLAGS_WDF) {
+ regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_WDF, 0);
+ handled = true;
+ }
+
return handled ? IRQ_HANDLED : IRQ_NONE;
}
@@ -503,6 +536,123 @@ static const struct pcf85x63_config pcf_85363_config = {
.num_nvram = 2
};
+/*
+ * This function sets the watchdog control register based on the timeout,
+ * clock selection and repeat mode settings. It prepares the value to
+ * write into the watchdog control register (CTRL_WDOG).
+ */
+static int pcf85363_wdt_reload(struct pcf85363_watchdog *wd)
+{
+ u8 val;
+
+ val = (wd->repeat ? WD_MODE_REPEAT : 0) |
+ ((wd->timeout_val & WD_TIMEOUT_MAX) << WD_TIMEOUT_SHIFT) |
+ (wd->clock_sel & WD_CLKSEL_MASK);
+
+ return regmap_write(wd->regmap, CTRL_WDOG, val);
+}
+
+static int pcf85363_wdt_start(struct watchdog_device *wdd)
+{
+ struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
+
+ return pcf85363_wdt_reload(wd);
+}
+
+static int pcf85363_wdt_stop(struct watchdog_device *wdd)
+{
+ struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
+
+ return regmap_write(wd->regmap, CTRL_WDOG, 0);
+}
+
+static int pcf85363_wdt_ping(struct watchdog_device *wdd)
+{
+ struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
+
+ regmap_update_bits(wd->regmap, CTRL_FLAGS, FLAGS_WDF, 0);
+
+ return pcf85363_wdt_reload(wd);
+}
+
+static int pcf85363_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
+
+ wd->timeout_val = clamp(timeout, WD_TIMEOUT_MIN, WD_TIMEOUT_MAX);
+ wdd->timeout = wd->timeout_val;
+
+ return pcf85363_wdt_reload(wd);
+}
+
+static const struct watchdog_info pcf85363_wdt_info = {
+ .identity = "PCF85363 Watchdog",
+ .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
+};
+
+static const struct watchdog_ops pcf85363_wdt_ops = {
+ .owner = THIS_MODULE,
+ .start = pcf85363_wdt_start,
+ .stop = pcf85363_wdt_stop,
+ .ping = pcf85363_wdt_ping,
+ .set_timeout = pcf85363_wdt_set_timeout,
+};
+
+static int pcf85363_watchdog_init(struct device *dev, struct regmap *regmap)
+{
+ struct pcf85363_watchdog *wd;
+ unsigned int timeout_sec;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_WATCHDOG))
+ return 0;
+
+ wd = devm_kzalloc(dev, sizeof(*wd), GFP_KERNEL);
+ if (!wd)
+ return -ENOMEM;
+
+ wd->regmap = regmap;
+ wd->dev = dev;
+
+ wd->wdd.info = &pcf85363_wdt_info;
+ wd->wdd.ops = &pcf85363_wdt_ops;
+ wd->wdd.min_timeout = WD_TIMEOUT_MIN;
+ wd->wdd.max_timeout = WD_TIMEOUT_MAX;
+ wd->wdd.parent = dev;
+ wd->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
+
+ ret = watchdog_init_timeout(&wd->wdd, 10, dev);
+ if (ret)
+ wd->wdd.timeout = clamp(10U, WD_TIMEOUT_MIN, WD_TIMEOUT_MAX);
+
+ timeout_sec = wd->wdd.timeout;
+
+ if (timeout_sec <= 2)
+ wd->clock_sel = WD_CLKSEL_16HZ;
+ else if (timeout_sec <= 8)
+ wd->clock_sel = WD_CLKSEL_4HZ;
+ else if (timeout_sec <= 16)
+ wd->clock_sel = WD_CLKSEL_1HZ;
+ else
+ wd->clock_sel = WD_CLKSEL_0_25HZ;
+
+ wd->repeat = true;
+
+ ret = regmap_update_bits(regmap, CTRL_FLAGS, FLAGS_WDF, 0);
+ if (ret) {
+ dev_err(dev, "failed to clear WDF:%d\n", ret);
+ return ret;
+ }
+
+ watchdog_set_drvdata(&wd->wdd, wd);
+
+ dev_dbg(dev, "pcf85363 watchdog registered (timeout=%us, clk_sel=%u)\n",
+ timeout_sec, wd->clock_sel);
+
+ return devm_watchdog_register_device(dev, &wd->wdd);
+}
+
/*
* Reads 6 bytes of timestamp data starting at the given base register,
* converts them from BCD to binary, and formats the result into a
@@ -684,20 +834,22 @@ static int pcf85363_probe(struct i2c_client *client)
PIN_IO_TSPM | PIN_IO_TSIM,
PIN_IO_TSPM | PIN_IO_TSIM);
+ ret = pcf85363_watchdog_init(dev, pcf85363->regmap);
+ if (ret)
+ dev_err_probe(dev, ret, "Watchdog init failed\n");
+
if (irq_a > 0 || wakeup_source)
device_init_wakeup(dev, true);
dev_set_drvdata(&pcf85363->rtc->dev, pcf85363);
- ret = devm_rtc_register_device(pcf85363->rtc);
-
+ ret = rtc_add_group(pcf85363->rtc, &pcf85363_attr_group);
if (ret)
- return dev_err_probe(dev, ret, "RTC registration failed\n");
-
- ret = sysfs_create_group(&pcf85363->rtc->dev.kobj, &pcf85363_attr_group);
+ return ret;
+ ret = devm_rtc_register_device(pcf85363->rtc);
if (ret)
- return dev_err_probe(dev, ret, "Timestamp sysfs creation failed\n");
+ return dev_err_probe(dev, ret, "RTC registration failed\n");
for (i = 0; i < config->num_nvram; i++) {
nvmem_cfg[i].priv = pcf85363;
--
2.25.1
^ permalink raw reply related
* [PATCH v3 2/5] rtc: pcf85363: support reporting battery switch-over via RTC_VL
From: Lakshay Piplani @ 2025-11-19 8:33 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree, wim, linux, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani
In-Reply-To: <20251119083336.2241142-1-lakshay.piplani@nxp.com>
Add battery switch-over reporting for PCF85263/PCF85363 using the standard
RTC_VL_* ioctl interface. When the backup supply takes over, the BSF flag
is exposed to userspace through RTC_VL_READ and can be cleared using
RTC_VL_CLR.
This allows applications to detect loss of main power without relying on
non-standard interfaces.
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
---
V2 -> V3:
- Split into separate patches as suggested:
- Battery switch-over detection.
- Timestamp recording for TS pin and battery switch-over events.
- Offset calibration.
- Watchdog timer (to be reviewed by watchdog maintainers).
- Dropped Alarm2 support
- Switched to rtc_add_group() for sysfs attributes
- Removed failure paths after RTC device registration as per subsystem guidelines.
V1 -> V2:
- Watchdog related changes due to removal of vendor specific properties
from device tree
* remove vendor DT knobs (enable/timeout/stepsize/repeat)
* use watchdog_init_timeout (with 10s default)
* derive clock_sel from final timeout
* default, repeat=true (repeat mode)
- Fixed uninitalised warning on 'ret' (reported by kernel test robot)
- Use dev_dbg instead of dev_info for debug related print messages
- Minor cleanup and commentsi
drivers/rtc/rtc-pcf85363.c | 49 ++++++++++++++++++++++++++++++++++++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index 540042b9eec8..c03d5a65c5f7 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -14,6 +14,7 @@
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/bcd.h>
+#include <linux/device.h>
#include <linux/of.h>
#include <linux/regmap.h>
@@ -295,23 +296,67 @@ static int pcf85363_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
{
struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
+ bool handled = false;
unsigned int flags;
int err;
err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
+
if (err)
return IRQ_NONE;
+ if (flags) {
+ dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s\n",
+ flags, (flags & FLAGS_A1F) ? " [A1F]" : "",
+ (flags & FLAGS_BSF) ? " [BSF]" : "");
+ }
+
if (flags & FLAGS_A1F) {
rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF | RTC_AF);
regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
- return IRQ_HANDLED;
+ handled = true;
}
- return IRQ_NONE;
+ if (flags & FLAGS_BSF) {
+ regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_BSF, 0);
+ handled = true;
+ }
+
+ return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static int pcf85363_rtc_ioctl(struct device *dev,
+ unsigned int cmd, unsigned long arg)
+{
+ struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
+ unsigned int val;
+ int ret;
+
+ switch (cmd) {
+ case RTC_VL_READ: {
+ u32 status = 0;
+
+ ret = regmap_read(pcf85363->regmap, CTRL_FLAGS, &val);
+
+ if (ret)
+ return ret;
+
+ if (val & FLAGS_BSF)
+ status |= RTC_VL_BACKUP_SWITCH;
+
+ return put_user(status, (u32 __user *)arg);
+ }
+
+ case RTC_VL_CLR:
+ return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_BSF, 0);
+
+ default:
+ return -ENOIOCTLCMD;
+ }
}
static const struct rtc_class_ops rtc_ops = {
+ .ioctl = pcf85363_rtc_ioctl,
.read_time = pcf85363_rtc_read_time,
.set_time = pcf85363_rtc_set_time,
.read_alarm = pcf85363_rtc_read_alarm,
--
2.25.1
^ permalink raw reply related
* [PATCH v3 3/5] rtc: pcf85363: add timestamp support with configurable timestamp mode
From: Lakshay Piplani @ 2025-11-19 8:33 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree, wim, linux, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani
In-Reply-To: <20251119083336.2241142-1-lakshay.piplani@nxp.com>
Add support for the timestamp capture registers available on PCF85263 and
PCF85363. The registers latch the current time when selected events occur,
such as TS pin activation or battery switch-over.
The capture source can be configured via the nxp,timestamp-mode device
tree property, and latched values are exported through read-only sysfs
attributes.
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
---
V2 -> V3:
- Split into separate patches as suggested:
- Battery switch-over detection.
- Timestamp recording for TS pin and battery switch-over events.
- Offset calibration.
- Watchdog timer (to be reviewed by watchdog maintainers).
- Dropped Alarm2 support
- Switched to rtc_add_group() for sysfs attributes
- Removed failure paths after RTC device registration as per subsystem guidelines.
V1 -> V2:
- Watchdog related changes due to removal of vendor specific properties
from device tree
* remove vendor DT knobs (enable/timeout/stepsize/repeat)
* use watchdog_init_timeout (with 10s default)
* derive clock_sel from final timeout
* default, repeat=true (repeat mode)
- Fixed uninitalised warning on 'ret' (reported by kernel test robot)
- Use dev_dbg instead of dev_info for debug related print messages
- Minor cleanup and comments
drivers/rtc/rtc-pcf85363.c | 210 +++++++++++++++++++++++++++++++------
1 file changed, 176 insertions(+), 34 deletions(-)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index c03d5a65c5f7..a8b4f48d9894 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -101,19 +101,31 @@
#define PIN_IO_INTA_OUT 2
#define PIN_IO_INTA_HIZ 3
+#define PIN_IO_TSPM GENMASK(3, 2)
+#define PIN_IO_TSIM BIT(4)
+
#define OSC_CAP_SEL GENMASK(1, 0)
#define OSC_CAP_6000 0x01
#define OSC_CAP_12500 0x02
#define STOP_EN_STOP BIT(0)
+#define RTCM_BIT BIT(4)
#define RESET_CPR 0xa4
#define NVRAM_SIZE 0x40
+#define TSR1_MASK 0x03
+#define TSR2_MASK 0x07
+#define TSR3_MASK 0x03
+#define TSR1_SHIFT 0
+#define TSR2_SHIFT 2
+#define TSR3_SHIFT 6
+
struct pcf85363 {
struct rtc_device *rtc;
struct regmap *regmap;
+ u8 ts_valid_flags;
};
struct pcf85x63_config {
@@ -306,8 +318,11 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
return IRQ_NONE;
if (flags) {
- dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s\n",
+ dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s%s%s%s\n",
flags, (flags & FLAGS_A1F) ? " [A1F]" : "",
+ (flags & FLAGS_TSR1F) ? " [TSR1F]" : "",
+ (flags & FLAGS_TSR2F) ? " [TSR2F]" : "",
+ (flags & FLAGS_TSR3F) ? " [TSR3F]" : "",
(flags & FLAGS_BSF) ? " [BSF]" : "");
}
@@ -317,6 +332,24 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
handled = true;
}
+ if (flags & FLAGS_TSR1F) {
+ regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_TSR1F, 0);
+ pcf85363->ts_valid_flags |= FLAGS_TSR1F;
+ handled = true;
+ }
+
+ if (flags & FLAGS_TSR2F) {
+ regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_TSR2F, 0);
+ pcf85363->ts_valid_flags |= FLAGS_TSR2F;
+ handled = true;
+ }
+
+ if (flags & FLAGS_TSR3F) {
+ regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_TSR3F, 0);
+ pcf85363->ts_valid_flags |= FLAGS_TSR3F;
+ handled = true;
+ }
+
if (flags & FLAGS_BSF) {
regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_BSF, 0);
handled = true;
@@ -424,11 +457,94 @@ static const struct pcf85x63_config pcf_85363_config = {
.num_nvram = 2
};
+/*
+ * Reads 6 bytes of timestamp data starting at the given base register,
+ * converts them from BCD to binary, and formats the result into a
+ * human-readable string in "YYYY-MM-DD HH:MM:SS" format.
+ */
+static int pcf85363_read_timestamp(struct pcf85363 *pcf85363, u8 base_reg, char *buf)
+{
+ struct rtc_time tm;
+ u8 regs[6];
+ int ret;
+
+ ret = regmap_bulk_read(pcf85363->regmap, base_reg, regs, sizeof(regs));
+
+ if (ret)
+ return ret;
+
+ tm.tm_sec = bcd2bin(regs[0]);
+ tm.tm_min = bcd2bin(regs[1]);
+ tm.tm_hour = bcd2bin(regs[2]);
+ tm.tm_mday = bcd2bin(regs[3]);
+ tm.tm_mon = bcd2bin(regs[4]) - 1;
+ tm.tm_year = bcd2bin(regs[5]) + 100;
+
+ return sysfs_emit(buf, "%04d-%02d-%02d %02d:%02d:%02d\n",
+ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+}
+
+/*
+ * Checks whether a specific timestamp flag is set. If so, reads and
+ * returns the formatted timestamp. Otherwise, returns "00-00-00 00:00:00".
+ */
+
+static ssize_t pcf85363_timestamp_show(struct device *dev, char *buf,
+ u8 timestamp_flag, u8 base_reg)
+{
+ struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
+
+ if (!(pcf85363->ts_valid_flags & timestamp_flag))
+ return sysfs_emit(buf, "00-00-00 00:00:00\n");
+
+ return pcf85363_read_timestamp(pcf85363, base_reg, buf);
+}
+
+static ssize_t timestamp1_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return pcf85363_timestamp_show(dev, buf, FLAGS_TSR1F, DT_TIMESTAMP1);
+}
+static DEVICE_ATTR_RO(timestamp1);
+
+static ssize_t timestamp2_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return pcf85363_timestamp_show(dev, buf, FLAGS_TSR2F, DT_TIMESTAMP2);
+}
+static DEVICE_ATTR_RO(timestamp2);
+
+static ssize_t timestamp3_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return pcf85363_timestamp_show(dev, buf, FLAGS_TSR3F, DT_TIMESTAMP3);
+}
+static DEVICE_ATTR_RO(timestamp3);
+
+static struct attribute *pcf85363_attrs[] = {
+ &dev_attr_timestamp1.attr,
+ &dev_attr_timestamp2.attr,
+ &dev_attr_timestamp3.attr,
+ NULL,
+};
+
+static const struct attribute_group pcf85363_attr_group = {
+ .attrs = pcf85363_attrs,
+};
+
static int pcf85363_probe(struct i2c_client *client)
{
- struct pcf85363 *pcf85363;
const struct pcf85x63_config *config = &pcf_85363_config;
const void *data = of_device_get_match_data(&client->dev);
+ struct device *dev = &client->dev;
+ struct pcf85363 *pcf85363;
+ int irq_a = client->irq;
+ bool wakeup_source;
+ int ret, i, err;
+ u32 tsr_mode[3];
+ u8 val;
+
static struct nvmem_config nvmem_cfg[] = {
{
.name = "pcf85x63-",
@@ -446,25 +562,43 @@ static int pcf85363_probe(struct i2c_client *client)
.reg_write = pcf85363_nvram_write,
},
};
- int ret, i, err;
- bool wakeup_source;
if (data)
config = data;
- pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
- GFP_KERNEL);
+ pcf85363 = devm_kzalloc(&client->dev, sizeof(*pcf85363), GFP_KERNEL);
if (!pcf85363)
return -ENOMEM;
+ pcf85363->ts_valid_flags = 0;
+
pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
- if (IS_ERR(pcf85363->regmap)) {
- dev_err(&client->dev, "regmap allocation failed\n");
- return PTR_ERR(pcf85363->regmap);
- }
+ if (IS_ERR(pcf85363->regmap))
+ return dev_err_probe(dev, PTR_ERR(pcf85363->regmap), "regmap init failed\n");
i2c_set_clientdata(client, pcf85363);
+ ret = regmap_update_bits(pcf85363->regmap, CTRL_FUNCTION, RTCM_BIT, 0);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable RTC mode\n");
+
+ if (!device_property_read_u32_array(dev, "nxp,timestamp-mode", tsr_mode, 3)) {
+ tsr_mode[0] &= TSR1_MASK;
+ tsr_mode[1] &= TSR2_MASK;
+ tsr_mode[2] &= TSR3_MASK;
+
+ val = (tsr_mode[2] << TSR3_SHIFT) |
+ (tsr_mode[1] << TSR2_SHIFT) |
+ (tsr_mode[0] << TSR1_SHIFT);
+
+ ret = regmap_write(pcf85363->regmap, DT_TS_MODE, val);
+ if (ret)
+ dev_warn(dev, "Failed to write timestamp mode register\n");
+
+ dev_dbg(dev, "Timestamp mode set: TSR1=0x%x TSR2=0x%x TSR3=0x%x\n",
+ tsr_mode[0], tsr_mode[1], tsr_mode[2]);
+ }
+
pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(pcf85363->rtc))
return PTR_ERR(pcf85363->rtc);
@@ -478,39 +612,47 @@ static int pcf85363_probe(struct i2c_client *client)
pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;
- wakeup_source = device_property_read_bool(&client->dev,
- "wakeup-source");
- if (client->irq > 0 || wakeup_source) {
- regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
- regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
- PIN_IO_INTAPM, PIN_IO_INTA_OUT);
- }
+ wakeup_source = device_property_read_bool(dev, "wakeup-source");
+
+ ret = regmap_write(pcf85363->regmap, CTRL_FLAGS, 0x00);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to clear CTRL_FLAGS\n");
- if (client->irq > 0) {
- unsigned long irqflags = IRQF_TRIGGER_LOW;
+ if (irq_a > 0) {
+ regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO, PIN_IO_INTAPM, PIN_IO_INTA_OUT);
+ ret = devm_request_threaded_irq(dev, irq_a, NULL,
+ pcf85363_rtc_handle_irq,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ "pcf85363-inta", client);
- if (dev_fwnode(&client->dev))
- irqflags = 0;
- ret = devm_request_threaded_irq(&client->dev, client->irq,
- NULL, pcf85363_rtc_handle_irq,
- irqflags | IRQF_ONESHOT,
- "pcf85363", client);
if (ret) {
- dev_warn(&client->dev,
- "unable to request IRQ, alarms disabled\n");
- client->irq = 0;
+ dev_err_probe(dev, ret, "INTA IRQ request failed\n");
+ irq_a = 0;
+ } else {
+ regmap_write(pcf85363->regmap, CTRL_INTA_EN, INT_BSIE
+ | INT_TSRIE);
}
}
- if (client->irq > 0 || wakeup_source) {
- device_init_wakeup(&client->dev, true);
- set_bit(RTC_FEATURE_ALARM, pcf85363->rtc->features);
- } else {
- clear_bit(RTC_FEATURE_ALARM, pcf85363->rtc->features);
- }
+ regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
+ PIN_IO_TSPM | PIN_IO_TSIM,
+ PIN_IO_TSPM | PIN_IO_TSIM);
+
+ if (irq_a > 0 || wakeup_source)
+ device_init_wakeup(dev, true);
+
+ dev_set_drvdata(&pcf85363->rtc->dev, pcf85363);
ret = devm_rtc_register_device(pcf85363->rtc);
+ if (ret)
+ return dev_err_probe(dev, ret, "RTC registration failed\n");
+
+ ret = sysfs_create_group(&pcf85363->rtc->dev.kobj, &pcf85363_attr_group);
+
+ if (ret)
+ return dev_err_probe(dev, ret, "Timestamp sysfs creation failed\n");
+
for (i = 0; i < config->num_nvram; i++) {
nvmem_cfg[i].priv = pcf85363;
devm_rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
--
2.25.1
^ permalink raw reply related
* [PATCH v3 4/5] rtc: pcf85363: add oscillator offset calibration support
From: Lakshay Piplani @ 2025-11-19 8:33 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree, wim, linux, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani
In-Reply-To: <20251119083336.2241142-1-lakshay.piplani@nxp.com>
Expose the oscillator offset register of PCF85263/PCF85363 through the
rtc_class_ops read_offset and set_offset callbacks, allowing userspace
to apply frequency correction for drift compensation.
The correction mode defaults to normal mode (OFFM = 0), where each step
introduces an offset of approximately 2.170 ppm and corrections occur
every 4 hours.
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
---
V2 -> V3:
- Split into separate patches as suggested:
- Battery switch-over detection.
- Timestamp recording for TS pin and battery switch-over events.
- Offset calibration.
- Watchdog timer (to be reviewed by watchdog maintainers).
- Dropped Alarm2 support
- Switched to rtc_add_group() for sysfs attributes
- Removed failure paths after RTC device registration as per subsystem guidelines.
V1 -> V2:
- Watchdog related changes due to removal of vendor specific properties
from device tree
* remove vendor DT knobs (enable/timeout/stepsize/repeat)
* use watchdog_init_timeout (with 10s default)
* derive clock_sel from final timeout
* default, repeat=true (repeat mode)
- Fixed uninitalised warning on 'ret' (reported by kernel test robot)
- Use dev_dbg instead of dev_info for debug related print messages
- Minor cleanup and comments
drivers/rtc/rtc-pcf85363.c | 46 ++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index a8b4f48d9894..3d733375187b 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -122,6 +122,11 @@
#define TSR2_SHIFT 2
#define TSR3_SHIFT 6
+#define OFFSET_SIGN_BIT 7
+#define OFFSET_MINIMUM -128
+#define OFFSET_MAXIMUM 127
+#define OFFSET_MASK 0xFF
+
struct pcf85363 {
struct rtc_device *rtc;
struct regmap *regmap;
@@ -358,6 +363,45 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
return handled ? IRQ_HANDLED : IRQ_NONE;
}
+/*
+ * Read the current RTC offset from the CTRL_OFFSET
+ * register. This value is an 8-bit signed 2's complement
+ * value that corrects osciallator drift.
+ */
+static int pcf85363_read_offset(struct device *dev, long *offset)
+{
+ struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(pcf85363->regmap, CTRL_OFFSET, &val);
+
+ if (ret)
+ return ret;
+
+ *offset = sign_extend32(val & OFFSET_MASK, OFFSET_SIGN_BIT);
+
+ return 0;
+}
+
+/*
+ * Write an oscillator offset correction value to
+ * the CTRL_OFFSET register. The valid range is
+ * -128 to 127 (8-bit signed), typically used to fine
+ * tune accuracy.
+ */
+static int pcf85363_set_offset(struct device *dev, long offset)
+{
+ struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
+
+ if (offset < OFFSET_MINIMUM || offset > OFFSET_MAXIMUM) {
+ dev_warn(dev, "Offset out of range: %ld\n", offset);
+ return -ERANGE;
+ }
+
+ return regmap_write(pcf85363->regmap, CTRL_OFFSET, offset & OFFSET_MASK);
+}
+
static int pcf85363_rtc_ioctl(struct device *dev,
unsigned int cmd, unsigned long arg)
{
@@ -395,6 +439,8 @@ static const struct rtc_class_ops rtc_ops = {
.read_alarm = pcf85363_rtc_read_alarm,
.set_alarm = pcf85363_rtc_set_alarm,
.alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
+ .read_offset = pcf85363_read_offset,
+ .set_offset = pcf85363_set_offset,
};
static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val,
--
2.25.1
^ permalink raw reply related
* Wiadomość z księgowości
From: Marek Poradecki @ 2025-11-19 9:01 UTC (permalink / raw)
To: linux-rtc
Dzień dobry,
pomagamy przedsiębiorcom wprowadzić model wymiany walut, który minimalizuje wahania kosztów przy rozliczeniach międzynarodowych.
Kiedyv możemy umówić się na 15-minutową rozmowę, aby zaprezentować, jak taki model mógłby działać w Państwa firmie - z gwarancją indywidualnych kursów i pełnym uproszczeniem płatności? Proszę o propozycję dogodnego terminu.
Pozdrawiam
Marek Poradecki
^ permalink raw reply
* Re: [PATCH v3 1/5] dt-bindings: rtc: nxp,pcf85363: add timestamp mode config
From: Krzysztof Kozlowski @ 2025-11-19 10:22 UTC (permalink / raw)
To: Lakshay Piplani, alexandre.belloni, linux-rtc, linux-kernel, robh,
krzk+dt, conor+dt, devicetree, wim, linux, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada
In-Reply-To: <20251119083336.2241142-1-lakshay.piplani@nxp.com>
On 19/11/2025 09:33, Lakshay Piplani wrote:
> NXP PCF85263/PCF85363 provides three timestamp registers (TSR1-TSR3)
> which latch the current time when a selected event occurs. Add a
> vendor specific property, nxp,timestamp-mode, to select the event
> source for each register.
>
> Also introduce a new header 'pcf85363-tsr.h' to expose
> macros for timestamp mode fields, improving readability
> of device tree file.
>
> Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
> ---
> V2 -> V3:
> - No changes in v3
> - Added Reviewed-by: Rob Herring <robh@kernel.org>
I don't see it. Please start using b4, so such trivialities won't affect
the process.
Best regards,
Krzysztof
^ permalink raw reply
* RE: [EXT] Re: [PATCH v3 1/5] dt-bindings: rtc: nxp,pcf85363: add timestamp mode config
From: Lakshay Piplani @ 2025-11-19 11:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, alexandre.belloni@bootlin.com,
linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, wim@linux-watchdog.org,
linux@roeck-us.net, linux-watchdog@vger.kernel.org
Cc: Vikash Bansal, Priyanka Jain, Shashank Rebbapragada
In-Reply-To: <0bc4d069-29bf-4d22-9a38-f9f6222fc07d@kernel.org>
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Wednesday, November 19, 2025 3:53 PM
> To: Lakshay Piplani <lakshay.piplani@nxp.com>;
> alexandre.belloni@bootlin.com; linux-rtc@vger.kernel.org; linux-
> kernel@vger.kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; devicetree@vger.kernel.org; wim@linux-watchdog.org;
> linux@roeck-us.net; linux-watchdog@vger.kernel.org
> Cc: Vikash Bansal <vikash.bansal@nxp.com>; Priyanka Jain
> <priyanka.jain@nxp.com>; Shashank Rebbapragada
> <shashank.rebbapragada@nxp.com>
> Subject: [EXT] Re: [PATCH v3 1/5] dt-bindings: rtc: nxp,pcf85363: add
> timestamp mode config
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> On 19/11/2025 09:33, Lakshay Piplani wrote:
> > NXP PCF85263/PCF85363 provides three timestamp registers (TSR1-TSR3)
> > which latch the current time when a selected event occurs. Add a
> > vendor specific property, nxp,timestamp-mode, to select the event
> > source for each register.
> >
> > Also introduce a new header 'pcf85363-tsr.h' to expose macros for
> > timestamp mode fields, improving readability of device tree file.
> >
> > Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
> > ---
> > V2 -> V3:
> > - No changes in v3
> > - Added Reviewed-by: Rob Herring <robh@kernel.org>
>
> I don't see it. Please start using b4, so such trivialities won't affect the process.
>
> Best regards,
> Krzysztof
Hi Krzysztof,
Thanks for pointing that out.
I mistakenly mentioned the Reviewed-by tag in the changelog but forgot to include it in the actual commit. I’ll make sure to add it in the v4 DT patch and start using b4 for preparing future revisions to avoid such issues.
Best regards,
Lakshay
^ permalink raw reply
* Re: [PATCH v3 5/5] rtc: pcf85363: add watchdog support with configurable step size
From: Guenter Roeck @ 2025-11-19 15:37 UTC (permalink / raw)
To: Lakshay Piplani, alexandre.belloni, linux-rtc, linux-kernel, robh,
krzk+dt, conor+dt, devicetree, wim, linux-watchdog
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada
In-Reply-To: <20251119083336.2241142-5-lakshay.piplani@nxp.com>
On 11/19/25 00:33, Lakshay Piplani wrote:
> Add watchdog timer support to PCF85263/PCF85363 using the linux watchdog
> subsystem. The driver programs the hardware watchdog timeout based on
> the requested period.
>
> Also use rtc_add_group() instead of sysfs_create_group() to register
> timestamp attributes under the RTC class device (/sys/class/rtc/rtcX).
>
> Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
> ---
> V2 -> V3:
> - Split into separate patches as suggested:
> - Battery switch-over detection.
> - Timestamp recording for TS pin and battery switch-over events.
> - Offset calibration.
> - Watchdog timer (to be reviewed by watchdog maintainers).
> - Dropped Alarm2 support
> - Switched to rtc_add_group() for sysfs attributes
> - Removed failure paths after RTC device registration as per subsystem guidelines.
> V1 -> V2:
> - Watchdog related changes due to removal of vendor specific properties
> from device tree
> * remove vendor DT knobs (enable/timeout/stepsize/repeat)
> * use watchdog_init_timeout (with 10s default)
> * derive clock_sel from final timeout
> * default, repeat=true (repeat mode)
> - Fixed uninitalised warning on 'ret' (reported by kernel test robot)
> - Use dev_dbg instead of dev_info for debug related print messages
> - Minor cleanup and comments
>
> drivers/rtc/rtc-pcf85363.c | 168 +++++++++++++++++++++++++++++++++++--
> 1 file changed, 160 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
> index 3d733375187b..34d4c2e16774 100644
> --- a/drivers/rtc/rtc-pcf85363.c
> +++ b/drivers/rtc/rtc-pcf85363.c
> @@ -5,6 +5,10 @@
> * Driver for NXP PCF85363 real-time clock.
> *
> * Copyright (C) 2017 Eric Nelson
> + *
> + * Copyright 2025 NXP
> + * Added support for timestamps, battery switch-over,
> + * watchdog, offset calibration.
> */
> #include <linux/module.h>
> #include <linux/i2c.h>
> @@ -17,6 +21,8 @@
> #include <linux/device.h>
> #include <linux/of.h>
> #include <linux/regmap.h>
> +#include <linux/rtc.h>
> +#include <linux/watchdog.h>
>
> /*
> * Date/Time registers
> @@ -127,6 +133,18 @@
> #define OFFSET_MAXIMUM 127
> #define OFFSET_MASK 0xFF
>
> +#define WD_MODE_REPEAT BIT(7)
> +#define WD_TIMEOUT_MASK GENMASK(6, 2)
> +#define WD_TIMEOUT_SHIFT 2
> +#define WD_CLKSEL_MASK GENMASK(1, 0)
> +#define WD_CLKSEL_0_25HZ 0x00
> +#define WD_CLKSEL_1HZ 0x01
> +#define WD_CLKSEL_4HZ 0x02
> +#define WD_CLKSEL_16HZ 0x03
> +
> +#define WD_TIMEOUT_MIN 1
> +#define WD_TIMEOUT_MAX 0x1F
> +
> struct pcf85363 {
> struct rtc_device *rtc;
> struct regmap *regmap;
> @@ -138,6 +156,15 @@ struct pcf85x63_config {
> unsigned int num_nvram;
> };
>
> +struct pcf85363_watchdog {
> + struct watchdog_device wdd;
> + struct regmap *regmap;
> + struct device *dev;
> + u8 timeout_val;
> + u8 clock_sel;
> + bool repeat;
> +};
> +
> static int pcf85363_load_capacitance(struct pcf85363 *pcf85363, struct device_node *node)
> {
> u32 load = 7000;
> @@ -323,12 +350,13 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
> return IRQ_NONE;
>
> if (flags) {
> - dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s%s%s%s\n",
> + dev_dbg(&pcf85363->rtc->dev, "IRQ flags: 0x%02x%s%s%s%s%s%s\n",
> flags, (flags & FLAGS_A1F) ? " [A1F]" : "",
> (flags & FLAGS_TSR1F) ? " [TSR1F]" : "",
> (flags & FLAGS_TSR2F) ? " [TSR2F]" : "",
> (flags & FLAGS_TSR3F) ? " [TSR3F]" : "",
> - (flags & FLAGS_BSF) ? " [BSF]" : "");
> + (flags & FLAGS_BSF) ? " [BSF]" : "",
> + (flags & FLAGS_WDF) ? " [WDF]" : "");
> }
>
> if (flags & FLAGS_A1F) {
> @@ -360,6 +388,11 @@ static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
> handled = true;
> }
>
> + if (flags & FLAGS_WDF) {
> + regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_WDF, 0);
> + handled = true;
> + }
> +
> return handled ? IRQ_HANDLED : IRQ_NONE;
> }
>
> @@ -503,6 +536,123 @@ static const struct pcf85x63_config pcf_85363_config = {
> .num_nvram = 2
> };
>
> +/*
> + * This function sets the watchdog control register based on the timeout,
> + * clock selection and repeat mode settings. It prepares the value to
> + * write into the watchdog control register (CTRL_WDOG).
> + */
> +static int pcf85363_wdt_reload(struct pcf85363_watchdog *wd)
> +{
> + u8 val;
> +
> + val = (wd->repeat ? WD_MODE_REPEAT : 0) |
> + ((wd->timeout_val & WD_TIMEOUT_MAX) << WD_TIMEOUT_SHIFT) |
> + (wd->clock_sel & WD_CLKSEL_MASK);
> +
> + return regmap_write(wd->regmap, CTRL_WDOG, val);
> +}
> +
> +static int pcf85363_wdt_start(struct watchdog_device *wdd)
> +{
> + struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
> +
> + return pcf85363_wdt_reload(wd);
> +}
> +
> +static int pcf85363_wdt_stop(struct watchdog_device *wdd)
> +{
> + struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
> +
> + return regmap_write(wd->regmap, CTRL_WDOG, 0);
> +}
> +
> +static int pcf85363_wdt_ping(struct watchdog_device *wdd)
> +{
> + struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
> +
> + regmap_update_bits(wd->regmap, CTRL_FLAGS, FLAGS_WDF, 0);
> +
> + return pcf85363_wdt_reload(wd);
> +}
> +
> +static int pcf85363_wdt_set_timeout(struct watchdog_device *wdd,
> + unsigned int timeout)
> +{
> + struct pcf85363_watchdog *wd = watchdog_get_drvdata(wdd);
> +
> + wd->timeout_val = clamp(timeout, WD_TIMEOUT_MIN, WD_TIMEOUT_MAX);
> + wdd->timeout = wd->timeout_val;
> +
> + return pcf85363_wdt_reload(wd);
> +}
> +
> +static const struct watchdog_info pcf85363_wdt_info = {
> + .identity = "PCF85363 Watchdog",
> + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
> +};
> +
> +static const struct watchdog_ops pcf85363_wdt_ops = {
> + .owner = THIS_MODULE,
> + .start = pcf85363_wdt_start,
> + .stop = pcf85363_wdt_stop,
> + .ping = pcf85363_wdt_ping,
> + .set_timeout = pcf85363_wdt_set_timeout,
> +};
> +
> +static int pcf85363_watchdog_init(struct device *dev, struct regmap *regmap)
> +{
> + struct pcf85363_watchdog *wd;
> + unsigned int timeout_sec;
> + int ret;
> +
> + if (!IS_ENABLED(CONFIG_WATCHDOG))
> + return 0;
> +
> + wd = devm_kzalloc(dev, sizeof(*wd), GFP_KERNEL);
> + if (!wd)
> + return -ENOMEM;
> +
> + wd->regmap = regmap;
> + wd->dev = dev;
> +
> + wd->wdd.info = &pcf85363_wdt_info;
> + wd->wdd.ops = &pcf85363_wdt_ops;
> + wd->wdd.min_timeout = WD_TIMEOUT_MIN;
> + wd->wdd.max_timeout = WD_TIMEOUT_MAX;
> + wd->wdd.parent = dev;
> + wd->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
> +
> + ret = watchdog_init_timeout(&wd->wdd, 10, dev);
Calling watchdog_init_timeout() with a value other than 0 means that
a parameter from devicetree won't be accepted. Calling it with a fixed
value is usually pointless unless the value is out of the valid range,
which by itself would be pointless.
watchdog_init_timeout() is normally called to pass and validate a module
parameter or to pick a timeout from devicetree. Calling it with a constant
value other than 0 is unnecessary.
> + if (ret)
> + wd->wdd.timeout = clamp(10U, WD_TIMEOUT_MIN, WD_TIMEOUT_MAX);
So if 10 seconds is invalid, 10 is clamped to [1, 31] and applied directly.
That is an odd and complicated way of setting the timeout to 10 seconds.
If you don't want a timeout value from devicetree to be accepted, just make this
wd->wdd.timeout = 10;
and do not call watchdog_init_timeout() in the first place.
> +
> + timeout_sec = wd->wdd.timeout;
> +
> + if (timeout_sec <= 2)
> + wd->clock_sel = WD_CLKSEL_16HZ;
> + else if (timeout_sec <= 8)
> + wd->clock_sel = WD_CLKSEL_4HZ;
> + else if (timeout_sec <= 16)
> + wd->clock_sel = WD_CLKSEL_1HZ;
> + else
> + wd->clock_sel = WD_CLKSEL_0_25HZ;
> +
This seems an odd location for this code. What if the timeout changes
later on to one of the other values ?
Also, the timeout is set to a fixed value of 10. That means the above
can be simplified to
wd->clock_sel = WD_CLKSEL_1HZ;
... and that in turn means that the variable is pointless, and that
WD_CLKSEL_1HZ could be used as constant instead.
Why all that complexity ? Am I missing something ? I am quite concerned that
I may be missing trees in the forest, meaning that the real problems are hiding
behind the noise.
Guenter
> + wd->repeat = true;
What is the purpose of this variable ? It is always set to true.
You might as well drop it.
> +
> + ret = regmap_update_bits(regmap, CTRL_FLAGS, FLAGS_WDF, 0);
> + if (ret) {
> + dev_err(dev, "failed to clear WDF:%d\n", ret);
> + return ret;
> + }
> +
> + watchdog_set_drvdata(&wd->wdd, wd);
> +
> + dev_dbg(dev, "pcf85363 watchdog registered (timeout=%us, clk_sel=%u)\n",
> + timeout_sec, wd->clock_sel);
> +
> + return devm_watchdog_register_device(dev, &wd->wdd);
> +}
> +
> /*
> * Reads 6 bytes of timestamp data starting at the given base register,
> * converts them from BCD to binary, and formats the result into a
> @@ -684,20 +834,22 @@ static int pcf85363_probe(struct i2c_client *client)
> PIN_IO_TSPM | PIN_IO_TSIM,
> PIN_IO_TSPM | PIN_IO_TSIM);
>
> + ret = pcf85363_watchdog_init(dev, pcf85363->regmap);
> + if (ret)
> + dev_err_probe(dev, ret, "Watchdog init failed\n");
> +
> if (irq_a > 0 || wakeup_source)
> device_init_wakeup(dev, true);
>
> dev_set_drvdata(&pcf85363->rtc->dev, pcf85363);
>
> - ret = devm_rtc_register_device(pcf85363->rtc);
> -
> + ret = rtc_add_group(pcf85363->rtc, &pcf85363_attr_group);
> if (ret)
> - return dev_err_probe(dev, ret, "RTC registration failed\n");
> -
> - ret = sysfs_create_group(&pcf85363->rtc->dev.kobj, &pcf85363_attr_group);
> + return ret;
>
> + ret = devm_rtc_register_device(pcf85363->rtc);
> if (ret)
> - return dev_err_probe(dev, ret, "Timestamp sysfs creation failed\n");
> + return dev_err_probe(dev, ret, "RTC registration failed\n");
>
It is not entirely obvious how those changes are related to adding watchdog support
to this driver.
> for (i = 0; i < config->num_nvram; i++) {
> nvmem_cfg[i].priv = pcf85363;
^ permalink raw reply
* [PATCH v5 00/16] Support ROHM BD72720 PMIC
From: Matti Vaittinen @ 2025-11-20 8:19 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
[-- Attachment #1: Type: text/plain, Size: 4269 bytes --]
The ROHM BD72720 is a new power management IC for portable, battery
powered devices. It integrates 10 BUCKs and 11 LDOs, RTC, charger, LEDs,
GPIOs and a clock gate. To me the BD72720 seems like a successor to the
BD71828 and BD71815 PMICs.
This series depends on
5bff79dad20a ("power: supply: Add bd718(15/28/78) charger driver")
which is in power-supply tree, for-next. Thus, the series is based on
it.
The testing of v4 suffered some hardware-issues after I accidentally
enabled charging while the PMIC's battery pin was connected to the I/O
domain. Some heat was generated, not terribly lot smoke though...
After the incident I've had occasional I2C failures. I, however, suspect
the root cause is HW damage in I/O lines since changes in this revision
have been made to dt-bindings. It's still fair to note that though, as
my testing was impacted.
Revision history:
v4 => v5:
- dt-binding fixes as discussed in v4 reviews.
- Drop rohm,vdr-battery.yaml and add vdr properties to battery.yaml
- Drop 'rohm,' -vendor-prefix from vdr properties
- Link to v4:
https://lore.kernel.org/all/cover.1763022807.git.mazziesaccount@gmail.com/
More accurate changelog in individual patches
v3 => v4:
- dt-binding fixes to the BD72720 MFD example and regulator bindings
More accurate changelog in individual patches
v2 => v3:
- rebased to power-supply/for-next as dependencies are merged to there
- plenty of dt-binding changes as suggested by reviewers
- add new patch to better document existing 'trickle-charging' property
More accurate changelog in individual patches
RFCv1 => v2:
- Drop RFC status
- Use stacked regmaps to hide secondary map from the sub-drivers
- Quite a few styling fixes and improvements as suggested by
reviewers. More accurate changelog in individual patches.
- Link to v1:
https://lore.kernel.org/all/cover.1759824376.git.mazziesaccount@gmail.com/
---
Matti Vaittinen (16):
dt-bindings: regulator: ROHM BD72720
dt-bindings: battery: Clarify trickle-charge
dt-bindings: battery: Add trickle-charge upper limit
dt-bindings: battery: Voltage drop properties
dt-bindings: mfd: ROHM BD72720
dt-bindings: leds: bd72720: Add BD72720
mfd: rohm-bd71828: Use regmap_reg_range()
mfd: bd71828: Support ROHM BD72720
regulator: bd71828: rename IC specific entities
regulator: bd71828: Support ROHM BD72720
gpio: Support ROHM BD72720 gpios
clk: clk-bd718x7: Support BD72720 clk gate
rtc: bd70528: Support BD72720 rtc
power: supply: bd71828: Support wider register addresses
power: supply: bd71828-power: Support ROHM BD72720
MAINTAINERS: Add ROHM BD72720 PMIC
.../bindings/leds/rohm,bd71828-leds.yaml | 7 +-
.../bindings/mfd/rohm,bd72720-pmic.yaml | 339 ++++++
.../bindings/power/supply/battery.yaml | 33 +-
.../regulator/rohm,bd72720-regulator.yaml | 148 +++
MAINTAINERS | 2 +
drivers/clk/Kconfig | 4 +-
drivers/clk/clk-bd718x7.c | 10 +-
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-bd72720.c | 281 +++++
drivers/mfd/Kconfig | 18 +-
drivers/mfd/rohm-bd71828.c | 546 ++++++++-
drivers/power/supply/bd71828-power.c | 160 ++-
drivers/regulator/Kconfig | 8 +-
drivers/regulator/bd71828-regulator.c | 1025 ++++++++++++++++-
drivers/rtc/Kconfig | 3 +-
drivers/rtc/rtc-bd70528.c | 21 +-
include/linux/mfd/rohm-bd72720.h | 634 ++++++++++
include/linux/mfd/rohm-generic.h | 1 +
19 files changed, 3120 insertions(+), 130 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml
create mode 100644 drivers/gpio/gpio-bd72720.c
create mode 100644 include/linux/mfd/rohm-bd72720.h
base-commit: 8e8856396b54bea5c00a7ae88d87c6254aef2d94
--
2.51.1
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^ permalink raw reply
* [PATCH v5 01/16] dt-bindings: regulator: ROHM BD72720
From: Matti Vaittinen @ 2025-11-20 8:19 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 7242 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The ROHM BD72720 is a new PMIC with 10 BUCk and 11 LDO regulators.
The BD72720 is designed to support using the BUCK10 as a supply for
the LDOs 1 to 4. When the BUCK10 is used for this, it can be set to a
LDON_HEAD mode. In this mode, the BUCK10 voltage can't be controlled by
software, but the voltage is adjusted by PMIC to match the LDO1 .. LDO4
voltages with a given offset. Offset can be 50mV .. 300mV and is
changeable at 50mV steps.
Add 'ldon-head-microvolt' property to denote a board which is designed
to utilize the LDON_HEAD mode.
All other properties are already existing.
Add dt-binding doc for ROHM BD72720 regulators to make it usable.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
Revision history:
v4 =>
- No changes
v3 => v4:
- Drop type from ldon-head
- Fix the name patterns for regulator nodes and names
v2 => v3:
- drop unnecessary descriptions
- use microvolts for the 'ldon-head' dt-property
RFCv1 => v2:
- No changes
---
.../regulator/rohm,bd72720-regulator.yaml | 148 ++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml
new file mode 100644
index 000000000000..5518082129bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/rohm,bd72720-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD72720 Power Management Integrated Circuit regulators
+
+maintainers:
+ - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description: |
+ This module is part of the ROHM BD72720 MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml.
+
+ The regulator controller is represented as a sub-node of the PMIC node
+ on the device tree.
+
+ Regulator nodes should be named to BUCK_<number> and LDO_<number>.
+ The valid names for BD72720 regulator nodes are
+ buck1, buck2, buck3, buck4, buck5, buck6, buck7, buck8, buck9, buck10
+ ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10, ldo11
+
+patternProperties:
+ "^ldo([1-9]|1[0-1])$":
+ type: object
+ description:
+ Properties for single LDO regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-name:
+ pattern: "^ldo([1-9]|1[0-1])$"
+
+ rohm,dvs-run-voltage:
+ description:
+ PMIC default "RUN" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-idle-voltage:
+ description:
+ PMIC default "IDLE" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-suspend-voltage:
+ description:
+ PMIC default "SUSPEND" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-lpsr-voltage:
+ description:
+ PMIC default "deep-idle" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ # Supported default DVS states:
+ # ldo | run | idle | suspend | lpsr
+ # --------------------------------------------------------------
+ # 1, 2, 3, and 4 | supported | supported | supported | supported
+ # --------------------------------------------------------------
+ # 5 - 11 | supported (*)
+ # --------------------------------------------------------------
+ #
+ # (*) All states use same voltage but have own enable / disable
+ # settings. Voltage 0 can be specified for a state to make
+ # regulator disabled on that state.
+
+ unevaluatedProperties: false
+
+ "^buck([1-9]|10)$":
+ type: object
+ description:
+ Properties for single BUCK regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-name:
+ pattern: "^buck([1-9]|10)$"
+
+ rohm,ldon-head-microvolt:
+ description:
+ Set this on boards where BUCK10 is used to supply LDOs 1-4. The bucki
+ voltage will be changed by the PMIC to follow the LDO output voltages
+ with the offset voltage given here. This will improve the LDO efficiency.
+ minimum: 50000
+ maximum: 300000
+
+ rohm,dvs-run-voltage:
+ description:
+ PMIC default "RUN" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-idle-voltage:
+ description:
+ PMIC default "IDLE" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-suspend-voltage:
+ description:
+ PMIC default "SUSPEND" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-lpsr-voltage:
+ description:
+ PMIC default "deep-idle" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ # Supported default DVS states:
+ # buck | run | idle | suspend | lpsr
+ # --------------------------------------------------------------
+ # 1, 2, 3, and 4 | supported | supported | supported | supported
+ # --------------------------------------------------------------
+ # 5 - 10 | supported (*)
+ # --------------------------------------------------------------
+ #
+ # (*) All states use same voltage but have own enable / disable
+ # settings. Voltage 0 can be specified for a state to make
+ # regulator disabled on that state.
+
+ required:
+ - regulator-name
+
+ unevaluatedProperties: false
+
+additionalProperties: false
--
2.51.1
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* [PATCH v5 02/16] dt-bindings: battery: Clarify trickle-charge
From: Matti Vaittinen @ 2025-11-20 8:19 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2155 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The term 'trickle-charging' is used to describe a very slow charging
phase, where electrons "trickle-in" the battery.
There are two different use-cases for this type of charging. At least
some Li-Ion batteries can benefit from very slow, constant current,
pre-pre phase 'trickle-charging', if a battery is very empty.
Some other batteries use top-off phase 'trickle-charging', which is
different from the above case.
The battery bindings use the term 'trickle-charge' without specifying
which of the use-cases properties are addressing. This has already
caused some confusion.
Clarify that the 'trickle-charge-current-microamp' refers to the first
one, the "pre-pre" -charging use-case.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
Revision history:
v3 => :
- No changes
v2 => v3:
- New patch
---
.../devicetree/bindings/power/supply/battery.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/supply/battery.yaml b/Documentation/devicetree/bindings/power/supply/battery.yaml
index 491488e7b970..bfb7b716ae13 100644
--- a/Documentation/devicetree/bindings/power/supply/battery.yaml
+++ b/Documentation/devicetree/bindings/power/supply/battery.yaml
@@ -64,7 +64,12 @@ properties:
description: battery design capacity
trickle-charge-current-microamp:
- description: current for trickle-charge phase
+ description: current for trickle-charge phase.
+ Please note that the trickle-charging here, refers "wake-up" or
+ "pre-pre" -charging, for very empty batteries. Similar term is also
+ used for "maintenance" or "top-off" -charging of batteries (like
+ NiMh bq24400) - that is different and not controlled by this
+ property.
precharge-current-microamp:
description: current for pre-charge phase
--
2.51.1
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^ permalink raw reply related
* [PATCH v5 03/16] dt-bindings: battery: Add trickle-charge upper limit
From: Matti Vaittinen @ 2025-11-20 8:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1748 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
Some of the chargers for lithium-ion batteries use a trickle-charging as
a first charging phase for very empty batteries, to "wake-up" the battery.
Trickle-charging is a low current, constant current phase. After the
voltage of the very empty battery has reached an upper limit for
trickle charging, the pre-charge phase is started with a higher current.
Allow defining the upper limit for trickle charging voltage, after which
the charging should be changed to the pre-charging.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Revision history:
v3 => :
- No changes
v2 => v3:
- Clarify the 'trickle-charging' the property refers to is the
"pre-pre" -phase charging.
RFCv1 => v2:
- No changes
---
Documentation/devicetree/bindings/power/supply/battery.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/supply/battery.yaml b/Documentation/devicetree/bindings/power/supply/battery.yaml
index bfb7b716ae13..d1a2080557a0 100644
--- a/Documentation/devicetree/bindings/power/supply/battery.yaml
+++ b/Documentation/devicetree/bindings/power/supply/battery.yaml
@@ -71,6 +71,10 @@ properties:
NiMh bq24400) - that is different and not controlled by this
property.
+ tricklecharge-upper-limit-microvolt:
+ description: limit when to change to precharge from trickle charge
+ Trickle-charging here refers "wake-up" or "pre-pre" -charging.
+
precharge-current-microamp:
description: current for pre-charge phase
--
2.51.1
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^ permalink raw reply related
* [PATCH v5 04/16] dt-bindings: battery: Voltage drop properties
From: Matti Vaittinen @ 2025-11-20 8:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 4661 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
ROHM has developed a so called "zero-correction" -algorithm to improve
the fuel-gauging accuracy close to the point where battery is depleted.
This relies on battery specific "VDR" (voltage drop rate) tables, which
are measured from the battery, and which describe the voltage drop rate.
More thorough explanation about the "zero correction" and "VDR"
parameters is here:
https://lore.kernel.org/all/676253b9-ff69-7891-1f26-a8b5bb5a421b@fi.rohmeurope.com/
Document the VDR zero-correction specific battery properties used by the
BD71815, BD71828, BD72720 and some other ROHM chargers. (Note, charger
drivers aren't upstream yet).
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
Revision history:
v4 => v5:
- Move volt-drop parameters from rohm,vdr-battry,yaml to the
battery.yaml
- drop rohm, -prefix from volt-drop-* properties
- Drop the rohm,vdr-battry,yaml
- Add comment clarifying what the rohm,volt-drop-* properties are for
because this may no longer be obvious as they were moved to common
battery.yaml
- Drop Linus Walleij's rb-tag because the concept was changed
v3 => v4:
- No changes
v2 => v3:
- Constrain VDR threshold voltage to 48V
- Use standard '-bp' -suffix for the rohm,volt-drop-soc
RFCv1 => v2:
- Add units to rohm,volt-drop-soc (tenths of %)
- Give real temperatures matching the VDR tables, instead of vague
'high', 'normal', 'low', 'very low'. (Add table of temperatures and
use number matching the right temperature index in the VDR table name).
- Fix typoed 'algorithm' in commit message.
The parameters are describing the battery voltage drop rates - so they
are properties of the battery, not the charger. Thus they do not belong
in the charger node.
The right place for them is the battery node, which is described by the
generic "battery.yaml". There were some discussion whether these
properties should be in their own file, or if they should be added to
battery.yaml. Discussion can be found from:
https://lore.kernel.org/all/52b99bf7-bfea-4cee-aa57-4c13e87eaa0d@gmail.com/
This patch implements the volt-drop properties as generic (not vemdor
specific) properties in the battery.yaml. It's worth noting that these
properties are:
- Meaningful only for those charger drivers which have the VDR
algorithm implemented. (And even though the algorithm is not charger
specific, AFAICS, it is currently only used by some ROHM PMIC
drivers).
- Technique of measuring the VDR tables for a battery is not widely
known. AFAICS, only folks at ROHM are measuring those for some
customer products. We do have those tables available for some of the
products, like Kobo e-readers though.
---
.../bindings/power/supply/battery.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/supply/battery.yaml b/Documentation/devicetree/bindings/power/supply/battery.yaml
index d1a2080557a0..8ebf05d9497c 100644
--- a/Documentation/devicetree/bindings/power/supply/battery.yaml
+++ b/Documentation/devicetree/bindings/power/supply/battery.yaml
@@ -128,6 +128,21 @@ properties:
- description: alert when battery temperature is lower than this value
- description: alert when battery temperature is higher than this value
+ # The volt-drop* -properties describe voltage-drop for a battery, described
+ # as VDROP in:
+ # https://patentimages.storage.googleapis.com/6c/f5/17/c1d901c220f6a9/US20150032394A1.pdf
+ volt-drop-thresh-microvolt:
+ description: Threshold for starting the VDR correction
+ maximum: 48000000
+
+ volt-drop-soc-bp:
+ description: Table of capacity values matching the values in VDR tables.
+ The value should be given as basis points, 1/100 of a percent.
+
+ volt-drop-temperatures-millicelsius:
+ description: An array containing the temperature in milli celsius, for each
+ of the VDR lookup table.
+
required:
- compatible
@@ -146,6 +161,13 @@ patternProperties:
- description: battery capacity percent
maximum: 100
+ '^volt-drop-[0-9]-microvolt':
+ description: Table of the voltage drop rate (VDR) values. Each entry in the
+ table should match a capacity value in the volt-drop-soc table.
+ Furthermore, the values should be obtained for the temperature given in
+ volt-drop-temperatures-millicelsius table at index matching the
+ number in this table's name.
+
additionalProperties: false
examples:
--
2.51.1
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* [PATCH v5 05/16] dt-bindings: mfd: ROHM BD72720
From: Matti Vaittinen @ 2025-11-20 8:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 13925 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The ROHM BD72720 is a power management IC integrating regulators, GPIOs,
charger, LEDs, RTC and a clock gate.
Add dt-binding doc for ROHM BD72720.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
Revision history:
v4 => v5:
- drop rohm, -prefix from vdr parameters
- Link to battery.yaml, not to rohm,vdr-battry.yaml which was removed
v3 => v4:
- Fix typo from the reference to regulator binding
- Fix Rsense limits to micro Ohms
- Fix compatible string in the example
- Fix regulator node names (to lower-case) in the example
- Add the missing regulator nodes to the example
v2 => v3:
- Styling
- Document all pin functions
- use pattern-properties
- re-use existing Rsense binding
- correct the example
RFCv1 => v2:
- Typofixes
---
.../bindings/mfd/rohm,bd72720-pmic.yaml | 339 ++++++++++++++++++
1 file changed, 339 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
new file mode 100644
index 000000000000..9f42097dfbac
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
@@ -0,0 +1,339 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rohm,bd72720-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD72720 Power Management Integrated Circuit
+
+maintainers:
+ - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description:
+ BD72720 is a single-chip power management IC for battery-powered portable
+ devices. The BD72720 integrates 10 bucks and 11 LDOs, and a 3000 mA
+ switching charger. The IC also includes a Coulomb counter, a real-time
+ clock (RTC), GPIOs and a 32.768 kHz clock gate.
+
+# In addition to the properties found from the charger node, the ROHM BD72720
+# uses properties from a static battery node. Please see the:
+# Documentation/devicetree/bindings/power/supply/battery.yaml
+#
+# Following properties are used
+# when present:
+#
+# charge-full-design-microamp-hours: Battry capacity in mAh
+# voltage-max-design-microvolt: Maximum voltage
+# voltage-min-design-microvolt: Minimum voltage system is still operating.
+# degrade-cycle-microamp-hours: Capacity lost due to aging at each full
+# charge cycle.
+# ocv-capacity-celsius: Array of OCV table temperatures. 1/table.
+# ocv-capacity-table-<N>: Table of OCV voltage/SOC pairs. Corresponds
+# N.th temperature in ocv-capacity-celsius
+#
+# volt-drop-thresh-microvolt: Threshold for starting the VDR correction
+# volt-drop-soc: Table of capacity values matching the
+# values in VDR tables.
+#
+# volt-drop-temperatures-millicelsius: Temperatures corresponding to the volage
+# drop values given in volt-drop-[0-9]-microvolt
+#
+# volt-drop-[0-9]-microvolt: VDR table for a temperature specified in
+# volt-drop-temperatures-millicelsius
+#
+# VDR tables are (usually) determined for a specific battery by ROHM.
+# The battery node would then be referred from the charger node:
+#
+# monitored-battery = <&battery>;
+
+properties:
+ compatible:
+ const: rohm,bd72720
+
+ reg:
+ description:
+ I2C slave address.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description:
+ The first cell is the pin number and the second cell is used to specify
+ flags. See the gpio binding document for more information.
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ const: bd71828-32k-out
+
+ rohm,clkout-open-drain:
+ description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 1
+
+ rohm,charger-sense-resistor-micro-ohms:
+ minimum: 10000
+ maximum: 50000
+ description:
+ BD72720 has a SAR ADC for measuring charging currents. External sense
+ resistor (RSENSE in data sheet) should be used. If some other but
+ 30 mOhm resistor is used the resistance value should be given here in
+ micro Ohms.
+
+ regulators:
+ $ref: /schemas/regulator/rohm,bd72720-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+ leds:
+ $ref: /schemas/leds/rohm,bd71828-leds.yaml
+
+ rohm,pin-fault_b:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ BD72720 has an OTP option to use fault_b-pin for different
+ purposes. Set this property accordingly. OTP options are
+ OTP0 - bi-directional FAULT_B or READY indicator depending on a
+ 'sub option'
+ OTP1 - GPO
+ OTP2 - Power sequencer output.
+ enum:
+ - faultb
+ - readyind
+ - gpo
+ - pwrseq
+
+patternProperties:
+ "^rohm,pin-dvs[0-1]$":
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ BD72720 has 4 different OTP options to determine the use of dvs<X>-pins.
+ OTP0 - regulator RUN state control.
+ OTP1 - GPI.
+ OTP2 - GPO.
+ OTP3 - Power sequencer output.
+ This property specifies the use of the pin.
+ enum:
+ - dvs-input
+ - gpi
+ - gpo
+ - pwrseq
+
+ "^rohm,pin-exten[0-1]$":
+ $ref: /schemas/types.yaml#/definitions/string
+ description: BD72720 has an OTP option to use exten0-pin for different
+ purposes. Set this property accordingly.
+ OTP0 - GPO
+ OTP1 - Power sequencer output.
+ enum:
+ - gpo
+ - pwrseq
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - "#clock-cells"
+ - regulators
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/leds/common.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic: pmic@4b {
+ compatible = "rohm,bd72720";
+ reg = <0x4b>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ clocks = <&osc 0>;
+ #clock-cells = <0>;
+ clock-output-names = "bd71828-32k-out";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rohm,pin-dvs0 = "gpi";
+ rohm,pin-dvs1 = "gpi";
+ rohm,pin-exten0 = "gpo";
+ rohm,pin-exten1 = "gpo";
+ rohm,pin-fault_b = "faultb";
+
+ rohm,charger-sense-resistor-micro-ohms = <10000>;
+
+ regulators {
+ buck1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2000000>;
+ };
+ buck4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ buck5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ buck6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-ramp-delay = <2500>;
+ rohm,dvs-run-voltage = <1700000>;
+ rohm,dvs-idle-voltage = <1>;
+ rohm,dvs-suspend-voltage = <1>;
+ rohm,dvs-lpsr-voltage = <0>;
+ regulator-boot-on;
+ };
+ buck9 {
+ regulator-name = "buck9";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-ramp-delay = <2500>;
+ rohm,dvs-run-voltage = <1700000>;
+ rohm,dvs-idle-voltage = <1>;
+ rohm,dvs-suspend-voltage = <1>;
+ rohm,dvs-lpsr-voltage = <0>;
+ regulator-boot-on;
+ };
+ buck10 {
+ regulator-name = "buck10";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-ramp-delay = <2500>;
+ rohm,dvs-run-voltage = <1700000>;
+ rohm,dvs-idle-voltage = <1>;
+ rohm,dvs-suspend-voltage = <1>;
+ rohm,dvs-lpsr-voltage = <0>;
+ regulator-boot-on;
+ };
+ ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ ldo10 {
+ regulator-name = "ldo10";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ ldo11 {
+ regulator-name = "ldo11";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ };
+
+ leds {
+ compatible = "rohm,bd71828-leds";
+
+ led-1 {
+ rohm,led-compatible = "bd71828-grnled";
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ led-2 {
+ rohm,led-compatible = "bd71828-ambled";
+ function = LED_FUNCTION_CHARGING;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+ };
+ };
+ };
--
2.51.1
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* [PATCH v5 06/16] dt-bindings: leds: bd72720: Add BD72720
From: Matti Vaittinen @ 2025-11-20 8:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2013 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
Add the ROHM BD72720 documentation to the binding documents.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Revision history:
RFCv1 =>:
- No changes
NOTE: The Linux LED driver does currently have: values
bd72720-grnled and bd72720-ambled for the rohm,led-compatible. These are
handled identically to the existing bd71828-grnled and bd71828-ambled
and should be removed from the driver. Thus they are not documented in
the binding document.
Furthermore, the BD72720 Linux driver does not use the compatible property
from the LED node. The Linux driver is load and probed based on the PMIC
compatible in the MFD node. Thus no compatible string for the BD72720
LED node is added.
---
.../devicetree/bindings/leds/rohm,bd71828-leds.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
index b7a3ef76cbf4..64cc40523e3d 100644
--- a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
+++ b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
@@ -10,11 +10,12 @@ maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
- This module is part of the ROHM BD71828 MFD device. For more details
- see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml.
+ This module is part of the ROHM BD71828 and BD72720 MFD device. For more
+ details see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+ and Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
The LED controller is represented as a sub-node of the PMIC node on the device
- tree.
+ tree. This should be located under "leds" - node in PMIC node.
The device has two LED outputs referred as GRNLED and AMBLED in data-sheet.
--
2.51.1
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^ permalink raw reply related
* [PATCH v5 07/16] mfd: rohm-bd71828: Use regmap_reg_range()
From: Matti Vaittinen @ 2025-11-20 8:21 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3326 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The regmap range tables tend to be somewhat verbose. Using the
regmap_reg_range() can make the definitions slightly mode compact.
Tidy the regmap range tables by using the regmap_reg_range().
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
Revision history:
v2 => :
- no changes
RFCv1 => v2:
- New patch
---
drivers/mfd/rohm-bd71828.c | 64 +++++++++++---------------------------
1 file changed, 18 insertions(+), 46 deletions(-)
diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c
index 84a64c3b9c9f..2a43005b67ee 100644
--- a/drivers/mfd/rohm-bd71828.c
+++ b/drivers/mfd/rohm-bd71828.c
@@ -157,55 +157,27 @@ static struct mfd_cell bd71828_mfd_cells[] = {
};
static const struct regmap_range bd71815_volatile_ranges[] = {
- {
- .range_min = BD71815_REG_SEC,
- .range_max = BD71815_REG_YEAR,
- }, {
- .range_min = BD71815_REG_CONF,
- .range_max = BD71815_REG_BAT_TEMP,
- }, {
- .range_min = BD71815_REG_VM_IBAT_U,
- .range_max = BD71815_REG_CC_CTRL,
- }, {
- .range_min = BD71815_REG_CC_STAT,
- .range_max = BD71815_REG_CC_CURCD_L,
- }, {
- .range_min = BD71815_REG_VM_BTMP_MON,
- .range_max = BD71815_REG_VM_BTMP_MON,
- }, {
- .range_min = BD71815_REG_INT_STAT,
- .range_max = BD71815_REG_INT_UPDATE,
- }, {
- .range_min = BD71815_REG_VM_VSYS_U,
- .range_max = BD71815_REG_REX_CTRL_1,
- }, {
- .range_min = BD71815_REG_FULL_CCNTD_3,
- .range_max = BD71815_REG_CCNTD_CHG_2,
- },
+ regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR),
+ regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP),
+ regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL),
+ regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L),
+ regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON),
+ regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE),
+ regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1),
+ regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2),
};
static const struct regmap_range bd71828_volatile_ranges[] = {
- {
- .range_min = BD71828_REG_PS_CTRL_1,
- .range_max = BD71828_REG_PS_CTRL_1,
- }, {
- .range_min = BD71828_REG_PS_CTRL_3,
- .range_max = BD71828_REG_PS_CTRL_3,
- }, {
- .range_min = BD71828_REG_RTC_SEC,
- .range_max = BD71828_REG_RTC_YEAR,
- }, {
- /*
- * For now make all charger registers volatile because many
- * needs to be and because the charger block is not that
- * performance critical.
- */
- .range_min = BD71828_REG_CHG_STATE,
- .range_max = BD71828_REG_CHG_FULL,
- }, {
- .range_min = BD71828_REG_INT_MAIN,
- .range_max = BD71828_REG_IO_STAT,
- },
+ regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1),
+ regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3),
+ regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR),
+ /*
+ * For now make all charger registers volatile because many
+ * needs to be and because the charger block is not that
+ * performance critical.
+ */
+ regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL),
+ regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT),
};
static const struct regmap_access_table bd71815_volatile_regs = {
--
2.51.1
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^ permalink raw reply related
* [PATCH v5 08/16] mfd: bd71828: Support ROHM BD72720
From: Matti Vaittinen @ 2025-11-20 8:22 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 50318 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The ROHM BD72720 is a power management IC which continues the BD71828
family of PMICs. Similarly to the BD71815 and BD71828, the BD72720
integrates regulators, charger, RTC, clock gate and GPIOs.
The main difference to the earlier PMICs is that the BD72720 has two
different I2C slave addresses. In addition to the registers behind the
'main I2C address', most of the charger (and to some extent LED) control
is done via registers behind a 'secondary I2C slave address', 0x4c.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
Revision history:
v2 =>:
- no changes
RFCv1 => v2: (Mostly addressed comments from Lee and Andreas)
- Use stacked regmaps to avoid platform data and the tango with
multiple regmaps in the power-supply driver
- Use regmap_reg_range()
- make it clear bd72720_irq_type_base is an array
- tab-out definitions in the bd72720 header
- minor styling
Note: This patch depends on the series: "power: supply: add charger for
BD71828" by Andreas:
https://lore.kernel.org/all/20250918-bd71828-charger-v5-0-851164839c28@kemnade.info/
There are some new variants being planned. Most notably, the BD73900
should be almost identical to the BD72720 - for everything else except
the charger block.
---
drivers/mfd/Kconfig | 18 +-
drivers/mfd/rohm-bd71828.c | 488 +++++++++++++++++++++++-
include/linux/mfd/rohm-bd72720.h | 634 +++++++++++++++++++++++++++++++
include/linux/mfd/rohm-generic.h | 1 +
4 files changed, 1126 insertions(+), 15 deletions(-)
create mode 100644 include/linux/mfd/rohm-bd72720.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6cec1858947b..61e238b316f4 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2211,20 +2211,22 @@ config MFD_ROHM_BD718XX
and emergency shut down as well as 32,768KHz clock output.
config MFD_ROHM_BD71828
- tristate "ROHM BD71828 and BD71815 Power Management IC"
+ tristate "ROHM BD718[15/28/79], BD72720 and BD73900 PMICs"
depends on I2C=y
depends on OF
select REGMAP_I2C
select REGMAP_IRQ
select MFD_CORE
help
- Select this option to get support for the ROHM BD71828 and BD71815
- Power Management ICs. BD71828GW and BD71815AGW are single-chip power
- management ICs mainly for battery-powered portable devices.
- The BD71828 integrates 7 buck converters and 7 LDOs. The BD71815
- has 5 bucks, 7 LDOs, and a boost for driving LEDs. Both ICs provide
- also a single-cell linear charger, a Coulomb counter, a real-time
- clock (RTC), GPIOs and a 32.768 kHz clock gate.
+ Select this option to get support for the ROHM BD71815, BD71828,
+ BD71879, BD72720 and BD73900 Power Management ICs. These are
+ single-chip power management ICs mainly for battery-powered portable
+ devices.
+ The BD71815 has 5 bucks, 7 LDOs, and a boost for driving LEDs.
+ The BD718[28/79] have 7 buck converters and 7 LDOs.
+ The BD72720 and the BD73900 have 10 bucks and 11 LDOs.
+ All ICs provide a single-cell linear charger, a Coulomb counter,
+ a real-time clock (RTC), GPIOs and a 32.768 kHz clock gate.
config MFD_ROHM_BD957XMUF
tristate "ROHM BD9576MUF and BD9573MUF Power Management ICs"
diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c
index 2a43005b67ee..2e546aa60ffd 100644
--- a/drivers/mfd/rohm-bd71828.c
+++ b/drivers/mfd/rohm-bd71828.c
@@ -2,7 +2,7 @@
//
// Copyright (C) 2019 ROHM Semiconductors
//
-// ROHM BD71828/BD71815 PMIC driver
+// ROHM BD718[15/28/79] and BD72720 PMIC driver
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
@@ -13,12 +13,29 @@
#include <linux/mfd/core.h>
#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
+#include <linux/mfd/rohm-bd72720.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/types.h>
+#define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \
+ [_irq] = { \
+ .reg_offset = (_stat_offset), \
+ .mask = (_mask), \
+ { \
+ .type_reg_offset = (_type_offset), \
+ .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \
+ .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \
+ .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \
+ .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \
+ .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \
+ .types_supported = IRQ_TYPE_EDGE_BOTH | \
+ IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \
+ }, \
+ }
+
static struct gpio_keys_button button = {
.code = KEY_POWER,
.gpio = -1,
@@ -43,6 +60,12 @@ static const struct resource bd71828_rtc_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"),
};
+static const struct resource bd72720_rtc_irqs[] = {
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"),
+};
+
static const struct resource bd71815_power_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"),
@@ -156,6 +179,74 @@ static struct mfd_cell bd71828_mfd_cells[] = {
},
};
+static const struct resource bd72720_power_irqs[] = {
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"),
+
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"),
+ DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"),
+};
+
+static const struct mfd_cell bd72720_mfd_cells[] = {
+ { .name = "bd72720-pmic", },
+ { .name = "bd72720-gpio", },
+ { .name = "bd72720-led", },
+ { .name = "bd72720-clk", },
+ {
+ .name = "bd72720-power",
+ .resources = bd72720_power_irqs,
+ .num_resources = ARRAY_SIZE(bd72720_power_irqs),
+ }, {
+ .name = "bd72720-rtc",
+ .resources = bd72720_rtc_irqs,
+ .num_resources = ARRAY_SIZE(bd72720_rtc_irqs),
+ }, {
+ .name = "gpio-keys",
+ .platform_data = &bd71828_powerkey_data,
+ .pdata_size = sizeof(bd71828_powerkey_data),
+ },
+};
+
static const struct regmap_range bd71815_volatile_ranges[] = {
regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR),
regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP),
@@ -180,6 +271,87 @@ static const struct regmap_range bd71828_volatile_ranges[] = {
regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT),
};
+static const struct regmap_range bd72720_volatile_ranges_4b[] = {
+ regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2),
+ regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE),
+ /* The state indicator bit changes when new state is reached */
+ regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1),
+ regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM),
+ regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT),
+ regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR),
+ regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC),
+};
+
+static const struct regmap_range bd72720_precious_ranges_4b[] = {
+ regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT),
+};
+
+/*
+ * The BD72720 is an odd beast in that it contains two separate sets of
+ * registers, both starting from address 0x0. The twist is that these "pages"
+ * are behind different I2C slave addresses. Most of the registers are behind
+ * a slave address 0x4b, which will be used as the "main" address for this
+ * device.
+ * Most of the charger related registers are located behind slave address 0x4c.
+ * It is tempting to push the dealing with the charger registers and the extra
+ * 0x4c device in power-supply driver - but perhaps it's better for the sake of
+ * the cleaner re-use to deal with setting up all of the regmaps here.
+ * Furthermore, the LED stuff may need access to both of these devices.
+ *
+ * Instead of providing one of the regmaps to sub-devices in MFD platform data,
+ * we create one more 'wrapper regmap' with custom read/write operations. These
+ * custom accessors will select which of the 'real' regmaps to use, based on
+ * the register address.
+ * The register addresses are 8-bit, so we add offset 0x100 to the addresses
+ * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the
+ * correct slave address based on the register address and call regmap_write()
+ * and regmap_read() using correct 'real' regmap. This way the registers of
+ * both of the slaves can be accessed using one 'wrapper' regmap.
+ *
+ * NOTE: The added offsets mean that the defined addresses for slave 0x4c must
+ * be used through the 'wrapper' regmap because the offset must be stripped
+ * from the register addresses. The 0x4b can be accessed both indirectly using
+ * the 'wrapper' regmap, and directly using the 'real' regmap.
+ */
+#define BD72720_SECONDARY_I2C_SLAVE 0x4c
+
+struct bd72720_regmaps {
+ struct regmap *map1_4b;
+ struct regmap *map2_4c;
+};
+
+/* Translate the slave 0x4c wrapper register address to a real one */
+#define BD72720_REG_UNWRAP(reg) ((reg) - 0x100)
+
+/* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */
+#define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \
+ regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg))
+static const struct regmap_range bd72720_volatile_ranges_4c[] = {
+ /* Status information */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN),
+ /*
+ * Under certain circumstances, write to some bits may be
+ * ignored
+ */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL),
+ /*
+ * TODO: Ensure this is used to advertise state, not (only?) to
+ * control it.
+ */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT),
+ /* Measured data */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L),
+ /* Self clearing bits */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL,
+ BD72720_REG_VM_VSYS_SA_MINMAX_CTRL),
+ /* Counters, self clearing bits */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL),
+ /* Self clearing bits */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL),
+ /* Self clearing bits */
+ BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL),
+};
+
static const struct regmap_access_table bd71815_volatile_regs = {
.yes_ranges = &bd71815_volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges),
@@ -190,6 +362,21 @@ static const struct regmap_access_table bd71828_volatile_regs = {
.n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges),
};
+static const struct regmap_access_table bd72720_volatile_regs_4b = {
+ .yes_ranges = &bd72720_volatile_ranges_4b[0],
+ .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b),
+};
+
+static const struct regmap_access_table bd72720_precious_regs_4b = {
+ .yes_ranges = &bd72720_precious_ranges_4b[0],
+ .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b),
+};
+
+static const struct regmap_access_table bd72720_volatile_regs_4c = {
+ .yes_ranges = &bd72720_volatile_ranges_4c[0],
+ .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c),
+};
+
static const struct regmap_config bd71815_regmap = {
.reg_bits = 8,
.val_bits = 8,
@@ -206,10 +393,79 @@ static const struct regmap_config bd71828_regmap = {
.cache_type = REGCACHE_MAPLE,
};
+static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val)
+{
+ struct bd72720_regmaps *maps = context;
+
+ if (reg < 0x100)
+ return regmap_write(maps->map1_4b, reg, val);
+
+ reg = BD72720_REG_UNWRAP(reg);
+
+ return regmap_write(maps->map2_4c, reg, val);
+}
+
+static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val)
+{
+ struct bd72720_regmaps *maps = context;
+
+ if (reg < 0x100)
+ return regmap_read(maps->map1_4b, reg, val);
+
+ reg = BD72720_REG_UNWRAP(reg);
+
+ return regmap_read(maps->map2_4c, reg, val);
+}
+
+static const struct regmap_config bd72720_wrapper_map_config = {
+ .name = "wrap-map",
+ .reg_bits = 9,
+ .val_bits = 8,
+ .max_register = BD72720_REG_IMPCHK_CTRL,
+ /*
+ * We don't want to duplicate caches. It would be a bit faster to
+ * have the cache in this 'wrapper regmap', and not in the 'real
+ * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would
+ * require all the subdevices to use the wrapper-map in order to be
+ * able to benefit from the cache.
+ * Currently most of the sub-devices use only the same slave-address
+ * as this MFD driver. Now, because we don't add the offset to the
+ * registers belonging to this slave, those devices can use either the
+ * wrapper map, or the bd72720_regmap_4b directly. This means majority
+ * of our sub devices don't need to care which regmap they get using
+ * the dev_get_regmap(). This unifies the code between the BD72720 and
+ * those variants which don't have this 'multiple slave addresses'
+ * -hassle.
+ * So, for a small performance penalty, we simplify the code for the
+ * sub-devices by having the caches in the wrapped regmaps and not here.
+ */
+ .cache_type = REGCACHE_NONE,
+ .reg_write = regmap_write_wrapper,
+ .reg_read = regmap_read_wrapper,
+};
+
+static const struct regmap_config bd72720_regmap_4b = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .volatile_table = &bd72720_volatile_regs_4b,
+ .precious_table = &bd72720_precious_regs_4b,
+ .max_register = BD72720_REG_INT_ETC2_SRC,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+static const struct regmap_config bd72720_regmap_4c = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .volatile_table = &bd72720_volatile_regs_4c,
+ .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL),
+ .cache_type = REGCACHE_MAPLE,
+};
+
/*
* Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
* access corect sub-IRQ registers based on bits that are set in main IRQ
- * register. BD71815 and BD71828 have same sub-register-block offests.
+ * register. BD71815 and BD71828 have same sub-register-block offests, the
+ * BD72720 has a different one.
*/
static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */
@@ -221,6 +477,15 @@ static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */
static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */
static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */
+static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */
+static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */
+static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */
+static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */
+static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */
+static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */
+static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */
+static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */
+
static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
@@ -232,6 +497,17 @@ static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
};
+static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = {
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets),
+ REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets),
+};
+
static const struct regmap_irq bd71815_irqs[] = {
REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK),
@@ -405,6 +681,117 @@ static const struct regmap_irq bd71828_irqs[] = {
REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK),
};
+static const struct regmap_irq bd72720_irqs[] = {
+ REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK),
+
+ REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK),
+
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK),
+/*
+ * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2
+ * pins. Eg, they may be wired to other devices which can then use the PMIC as
+ * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type
+ * specified. All of the types (falling, rising, and both edges as well as low
+ * and high levels) are supported.
+ */
+ BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0),
+ BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1),
+ REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK),
+ REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK),
+};
+
+static int bd72720_set_type_config(unsigned int **buf, unsigned int type,
+ const struct regmap_irq *irq_data,
+ int idx, void *irq_drv_data)
+{
+ const struct regmap_irq_type *t = &irq_data->type;
+
+ /*
+ * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register
+ * as logical OR of the type_falling_val and type_rising_val. This is
+ * not how the BD72720 implements this configuration, hence we need
+ * to handle this specific case separately.
+ */
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ buf[0][idx] &= ~t->type_reg_mask;
+ buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH;
+
+ return 0;
+ }
+
+ return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data);
+}
+
static const struct regmap_irq_chip bd71828_irq_chip = {
.name = "bd71828_irq",
.main_status = BD71828_REG_INT_MAIN,
@@ -437,6 +824,28 @@ static const struct regmap_irq_chip bd71815_irq_chip = {
.irq_reg_stride = 1,
};
+static const unsigned int bd72720_irq_type_base[] = {BD72720_REG_GPIO1_CTRL};
+
+static const struct regmap_irq_chip bd72720_irq_chip = {
+ .name = "bd72720_irq",
+ .main_status = BD72720_REG_INT_LVL1_STAT,
+ .irqs = &bd72720_irqs[0],
+ .num_irqs = ARRAY_SIZE(bd72720_irqs),
+ .status_base = BD72720_REG_INT_PS1_STAT,
+ .unmask_base = BD72720_REG_INT_PS1_EN,
+ .config_base = &bd72720_irq_type_base[0],
+ .num_config_bases = 1,
+ .num_config_regs = 2,
+ .set_type_config = bd72720_set_type_config,
+ .ack_base = BD72720_REG_INT_PS1_STAT,
+ .init_ack_masked = true,
+ .num_regs = 12,
+ .num_main_regs = 1,
+ .sub_reg_offsets = &bd72720_sub_irq_offsets[0],
+ .num_main_status_bits = 8,
+ .irq_reg_stride = 1,
+};
+
static int set_clk_mode(struct device *dev, struct regmap *regmap,
int clkmode_reg)
{
@@ -483,11 +892,40 @@ static void bd71828_remove_poweroff(void *data)
pm_power_off = NULL;
}
+static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c)
+{
+ struct bd72720_regmaps *maps;
+ struct i2c_client *secondary_i2c;
+
+ secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter,
+ BD72720_SECONDARY_I2C_SLAVE);
+ if (IS_ERR(secondary_i2c)) {
+ dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c),
+ "Failed to get secondary I2C\n");
+
+ return (struct regmap *)secondary_i2c;
+ }
+
+ maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL);
+ if (!maps)
+ return ERR_PTR(-ENOMEM);
+
+ maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b);
+ if (IS_ERR(maps->map1_4b))
+ return maps->map1_4b;
+
+ maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c);
+ if (IS_ERR(maps->map2_4c))
+ return maps->map2_4c;
+
+ return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config);
+}
+
static int bd71828_i2c_probe(struct i2c_client *i2c)
{
struct regmap_irq_chip_data *irq_data;
int ret;
- struct regmap *regmap;
+ struct regmap *regmap = NULL;
const struct regmap_config *regmap_config;
const struct regmap_irq_chip *irqchip;
unsigned int chip_type;
@@ -495,6 +933,7 @@ static int bd71828_i2c_probe(struct i2c_client *i2c)
int cells;
int button_irq;
int clkmode_reg;
+ int main_lvl_mask_reg = 0, main_lvl_val = 0;
if (!i2c->irq) {
dev_err(&i2c->dev, "No IRQ configured\n");
@@ -526,16 +965,34 @@ static int bd71828_i2c_probe(struct i2c_client *i2c)
*/
button_irq = 0;
break;
+ case ROHM_CHIP_TYPE_BD72720:
+ {
+ mfd = bd72720_mfd_cells;
+ cells = ARRAY_SIZE(bd72720_mfd_cells);
+
+ regmap = bd72720_do_regmaps(i2c);
+ if (IS_ERR(regmap))
+ return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
+ "Failed to initialize Regmap\n");
+
+ irqchip = &bd72720_irq_chip;
+ clkmode_reg = BD72720_REG_OUT32K;
+ button_irq = BD72720_INT_SHORTPUSH;
+ main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN;
+ main_lvl_val = BD72720_MASK_LVL1_EN_ALL;
+ break;
+ }
default:
dev_err(&i2c->dev, "Unknown device type");
return -EINVAL;
}
- regmap = devm_regmap_init_i2c(i2c, regmap_config);
- if (IS_ERR(regmap))
- return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
+ if (!regmap) {
+ regmap = devm_regmap_init_i2c(i2c, regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
"Failed to initialize Regmap\n");
-
+ }
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
IRQF_ONESHOT, 0, irqchip, &irq_data);
if (ret)
@@ -545,6 +1002,20 @@ static int bd71828_i2c_probe(struct i2c_client *i2c)
dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
irqchip->num_irqs);
+ /*
+ * On some ICs the main IRQ register has corresponding mask register.
+ * This is not handled by the regmap IRQ. Let's enable all the main
+ * level IRQs here. Further writes to the main level MASK is not
+ * needed because masking is handled by the per IRQ 2.nd level MASK
+ * registers. 2.nd level masks are handled by the regmap IRQ.
+ */
+ if (main_lvl_mask_reg) {
+ ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val);
+ if (ret) {
+ return dev_err_probe(&i2c->dev, ret,
+ "Failed to enable main level IRQs\n");
+ }
+ }
if (button_irq) {
ret = regmap_irq_get_virq(irq_data, button_irq);
if (ret < 0)
@@ -586,6 +1057,9 @@ static const struct of_device_id bd71828_of_match[] = {
}, {
.compatible = "rohm,bd71815",
.data = (void *)ROHM_CHIP_TYPE_BD71815,
+ }, {
+ .compatible = "rohm,bd72720",
+ .data = (void *)ROHM_CHIP_TYPE_BD72720,
},
{ },
};
diff --git a/include/linux/mfd/rohm-bd72720.h b/include/linux/mfd/rohm-bd72720.h
new file mode 100644
index 000000000000..42fcf8f81b2f
--- /dev/null
+++ b/include/linux/mfd/rohm-bd72720.h
@@ -0,0 +1,634 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2024 ROHM Semiconductors.
+ *
+ * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+ */
+
+#ifndef _MFD_BD72720_H
+#define _MFD_BD72720_H
+
+#include <linux/regmap.h>
+
+enum {
+ BD72720_BUCK1,
+ BD72720_BUCK2,
+ BD72720_BUCK3,
+ BD72720_BUCK4,
+ BD72720_BUCK5,
+ BD72720_BUCK6,
+ BD72720_BUCK7,
+ BD72720_BUCK8,
+ BD72720_BUCK9,
+ BD72720_BUCK10,
+ BD72720_BUCK11,
+ BD72720_LDO1,
+ BD72720_LDO2,
+ BD72720_LDO3,
+ BD72720_LDO4,
+ BD72720_LDO5,
+ BD72720_LDO6,
+ BD72720_LDO7,
+ BD72720_LDO8,
+ BD72720_LDO9,
+ BD72720_LDO10,
+ BD72720_LDO11,
+ BD72720_REGULATOR_AMOUNT,
+};
+
+/* BD72720 interrupts */
+#define BD72720_INT_LONGPUSH_MASK BIT(0)
+#define BD72720_INT_MIDPUSH_MASK BIT(1)
+#define BD72720_INT_SHORTPUSH_MASK BIT(2)
+#define BD72720_INT_PUSH_MASK BIT(3)
+#define BD72720_INT_HALL_DET_MASK BIT(4)
+#define BD72720_INT_HALL_TGL_MASK BIT(5)
+#define BD72720_INT_WDOG_MASK BIT(6)
+#define BD72720_INT_SWRESET_MASK BIT(7)
+#define BD72720_INT_SEQ_DONE_MASK BIT(0)
+#define BD72720_INT_PGFAULT_MASK BIT(4)
+#define BD72720_INT_BUCK1_DVS_MASK BIT(0)
+#define BD72720_INT_BUCK2_DVS_MASK BIT(1)
+#define BD72720_INT_BUCK3_DVS_MASK BIT(2)
+#define BD72720_INT_BUCK4_DVS_MASK BIT(3)
+#define BD72720_INT_BUCK5_DVS_MASK BIT(4)
+#define BD72720_INT_BUCK6_DVS_MASK BIT(5)
+#define BD72720_INT_BUCK7_DVS_MASK BIT(6)
+#define BD72720_INT_BUCK8_DVS_MASK BIT(7)
+#define BD72720_INT_BUCK9_DVS_MASK BIT(0)
+#define BD72720_INT_BUCK10_DVS_MASK BIT(1)
+#define BD72720_INT_LDO1_DVS_MASK BIT(4)
+#define BD72720_INT_LDO2_DVS_MASK BIT(5)
+#define BD72720_INT_LDO3_DVS_MASK BIT(6)
+#define BD72720_INT_LDO4_DVS_MASK BIT(7)
+#define BD72720_INT_VBUS_RMV_MASK BIT(0)
+#define BD72720_INT_VBUS_DET_MASK BIT(1)
+#define BD72720_INT_VBUS_MON_RES_MASK BIT(2)
+#define BD72720_INT_VBUS_MON_DET_MASK BIT(3)
+#define BD72720_INT_VSYS_MON_RES_MASK BIT(0)
+#define BD72720_INT_VSYS_MON_DET_MASK BIT(1)
+#define BD72720_INT_VSYS_UV_RES_MASK BIT(2)
+#define BD72720_INT_VSYS_UV_DET_MASK BIT(3)
+#define BD72720_INT_VSYS_LO_RES_MASK BIT(4)
+#define BD72720_INT_VSYS_LO_DET_MASK BIT(5)
+#define BD72720_INT_VSYS_OV_RES_MASK BIT(6)
+#define BD72720_INT_VSYS_OV_DET_MASK BIT(7)
+#define BD72720_INT_BAT_ILIM_MASK BIT(0)
+#define BD72720_INT_CHG_DONE_MASK BIT(1)
+#define BD72720_INT_EXTEMP_TOUT_MASK BIT(2)
+#define BD72720_INT_CHG_WDT_EXP_MASK BIT(3)
+#define BD72720_INT_BAT_MNT_OUT_MASK BIT(4)
+#define BD72720_INT_BAT_MNT_IN_MASK BIT(5)
+#define BD72720_INT_CHG_TRNS_MASK BIT(7)
+#define BD72720_INT_VBAT_MON_RES_MASK BIT(0)
+#define BD72720_INT_VBAT_MON_DET_MASK BIT(1)
+#define BD72720_INT_VBAT_SHT_RES_MASK BIT(2)
+#define BD72720_INT_VBAT_SHT_DET_MASK BIT(3)
+#define BD72720_INT_VBAT_LO_RES_MASK BIT(4)
+#define BD72720_INT_VBAT_LO_DET_MASK BIT(5)
+#define BD72720_INT_VBAT_OV_RES_MASK BIT(6)
+#define BD72720_INT_VBAT_OV_DET_MASK BIT(7)
+#define BD72720_INT_BAT_RMV_MASK BIT(0)
+#define BD72720_INT_BAT_DET_MASK BIT(1)
+#define BD72720_INT_DBAT_DET_MASK BIT(2)
+#define BD72720_INT_BAT_TEMP_TRNS_MASK BIT(3)
+#define BD72720_INT_LOBTMP_RES_MASK BIT(4)
+#define BD72720_INT_LOBTMP_DET_MASK BIT(5)
+#define BD72720_INT_OVBTMP_RES_MASK BIT(6)
+#define BD72720_INT_OVBTMP_DET_MASK BIT(7)
+#define BD72720_INT_OCUR1_RES_MASK BIT(0)
+#define BD72720_INT_OCUR1_DET_MASK BIT(1)
+#define BD72720_INT_OCUR2_RES_MASK BIT(2)
+#define BD72720_INT_OCUR2_DET_MASK BIT(3)
+#define BD72720_INT_OCUR3_RES_MASK BIT(4)
+#define BD72720_INT_OCUR3_DET_MASK BIT(5)
+#define BD72720_INT_CC_MON1_DET_MASK BIT(0)
+#define BD72720_INT_CC_MON2_DET_MASK BIT(1)
+#define BD72720_INT_CC_MON3_DET_MASK BIT(2)
+#define BD72720_INT_GPIO1_IN_MASK BIT(4)
+#define BD72720_INT_GPIO2_IN_MASK BIT(5)
+#define BD72720_INT_VF125_RES_MASK BIT(0)
+#define BD72720_INT_VF125_DET_MASK BIT(1)
+#define BD72720_INT_VF_RES_MASK BIT(2)
+#define BD72720_INT_VF_DET_MASK BIT(3)
+#define BD72720_INT_RTC0_MASK BIT(4)
+#define BD72720_INT_RTC1_MASK BIT(5)
+#define BD72720_INT_RTC2_MASK BIT(6)
+
+enum {
+ /*
+ * The IRQs excluding GPIO1 and GPIO2 are ordered in a same way as the
+ * respective IRQ bits in status and mask registers are ordered.
+ *
+ * The BD72720_INT_GPIO1_IN and BD72720_INT_GPIO2_IN are IRQs which can
+ * be used by other devices. Let's have GPIO1 and GPIO2 as first IRQs
+ * here so we can use the regmap-IRQ with standard device tree xlate
+ * while devices connected to the BD72720 IRQ input pins can refer to
+ * the first two interrupt numbers in their device tree. If we placed
+ * BD72720_INT_GPIO1_IN and BD72720_INT_GPIO2_IN after the CC_MON_DET
+ * interrupts (like they are in the registers), the devices using
+ * BD72720 as an IRQ parent should refer the interrupts starting with
+ * an offset which might not be trivial to understand.
+ */
+ BD72720_INT_GPIO1_IN,
+ BD72720_INT_GPIO2_IN,
+ BD72720_INT_LONGPUSH,
+ BD72720_INT_MIDPUSH,
+ BD72720_INT_SHORTPUSH,
+ BD72720_INT_PUSH,
+ BD72720_INT_HALL_DET,
+ BD72720_INT_HALL_TGL,
+ BD72720_INT_WDOG,
+ BD72720_INT_SWRESET,
+ BD72720_INT_SEQ_DONE,
+ BD72720_INT_PGFAULT,
+ BD72720_INT_BUCK1_DVS,
+ BD72720_INT_BUCK2_DVS,
+ BD72720_INT_BUCK3_DVS,
+ BD72720_INT_BUCK4_DVS,
+ BD72720_INT_BUCK5_DVS,
+ BD72720_INT_BUCK6_DVS,
+ BD72720_INT_BUCK7_DVS,
+ BD72720_INT_BUCK8_DVS,
+ BD72720_INT_BUCK9_DVS,
+ BD72720_INT_BUCK10_DVS,
+ BD72720_INT_LDO1_DVS,
+ BD72720_INT_LDO2_DVS,
+ BD72720_INT_LDO3_DVS,
+ BD72720_INT_LDO4_DVS,
+ BD72720_INT_VBUS_RMV,
+ BD72720_INT_VBUS_DET,
+ BD72720_INT_VBUS_MON_RES,
+ BD72720_INT_VBUS_MON_DET,
+ BD72720_INT_VSYS_MON_RES,
+ BD72720_INT_VSYS_MON_DET,
+ BD72720_INT_VSYS_UV_RES,
+ BD72720_INT_VSYS_UV_DET,
+ BD72720_INT_VSYS_LO_RES,
+ BD72720_INT_VSYS_LO_DET,
+ BD72720_INT_VSYS_OV_RES,
+ BD72720_INT_VSYS_OV_DET,
+ BD72720_INT_BAT_ILIM,
+ BD72720_INT_CHG_DONE,
+ BD72720_INT_EXTEMP_TOUT,
+ BD72720_INT_CHG_WDT_EXP,
+ BD72720_INT_BAT_MNT_OUT,
+ BD72720_INT_BAT_MNT_IN,
+ BD72720_INT_CHG_TRNS,
+ BD72720_INT_VBAT_MON_RES,
+ BD72720_INT_VBAT_MON_DET,
+ BD72720_INT_VBAT_SHT_RES,
+ BD72720_INT_VBAT_SHT_DET,
+ BD72720_INT_VBAT_LO_RES,
+ BD72720_INT_VBAT_LO_DET,
+ BD72720_INT_VBAT_OV_RES,
+ BD72720_INT_VBAT_OV_DET,
+ BD72720_INT_BAT_RMV,
+ BD72720_INT_BAT_DET,
+ BD72720_INT_DBAT_DET,
+ BD72720_INT_BAT_TEMP_TRNS,
+ BD72720_INT_LOBTMP_RES,
+ BD72720_INT_LOBTMP_DET,
+ BD72720_INT_OVBTMP_RES,
+ BD72720_INT_OVBTMP_DET,
+ BD72720_INT_OCUR1_RES,
+ BD72720_INT_OCUR1_DET,
+ BD72720_INT_OCUR2_RES,
+ BD72720_INT_OCUR2_DET,
+ BD72720_INT_OCUR3_RES,
+ BD72720_INT_OCUR3_DET,
+ BD72720_INT_CC_MON1_DET,
+ BD72720_INT_CC_MON2_DET,
+ BD72720_INT_CC_MON3_DET,
+ BD72720_INT_VF125_RES,
+ BD72720_INT_VF125_DET,
+ BD72720_INT_VF_RES,
+ BD72720_INT_VF_DET,
+ BD72720_INT_RTC0,
+ BD72720_INT_RTC1,
+ BD72720_INT_RTC2,
+};
+
+/*
+ * BD72720 Registers:
+ * The BD72720 has two sets of registers behind two different I2C slave
+ * addresses. "Common" registers being behind 0x4b, the charger registers
+ * being behind 0x4c.
+ */
+/* Registers behind I2C slave 0x4b */
+enum {
+ BD72720_REG_PRODUCT_ID,
+ BD72720_REG_MANUFACTURER_ID,
+ BD72720_REG_PMIC_REV_NUM,
+ BD72720_REG_NVM_REV_NUM,
+ BD72720_REG_BOOTSRC = 0x10,
+ BD72720_REG_RESETSRC_1,
+ BD72720_REG_RESETSRC_2,
+ BD72720_REG_RESETSRC_3,
+ BD72720_REG_RESETSRC_4,
+ BD72720_REG_RESETSRC_5,
+ BD72720_REG_RESETSRC_6,
+ BD72720_REG_RESETSRC_7,
+ BD72720_REG_POWER_STATE,
+ BD72720_REG_PS_CFG,
+ BD72720_REG_PS_CTRL_1,
+ BD72720_REG_PS_CTRL_2,
+ BD72720_REG_RCVCFG,
+ BD72720_REG_RCVNUM,
+ BD72720_REG_CRDCFG,
+ BD72720_REG_REX_CTRL,
+
+ BD72720_REG_BUCK1_ON,
+ BD72720_REG_BUCK1_MODE,
+ /* Deep idle vsel */
+ BD72720_REG_BUCK1_VSEL_DI,
+ /* Idle vsel */
+ BD72720_REG_BUCK1_VSEL_I,
+ /* Suspend vsel */
+ BD72720_REG_BUCK1_VSEL_S,
+ /* Run boot vsel */
+ BD72720_REG_BUCK1_VSEL_RB,
+ /* Run0 ... run3 vsel */
+ BD72720_REG_BUCK1_VSEL_RB0,
+ BD72720_REG_BUCK1_VSEL_RB1,
+ BD72720_REG_BUCK1_VSEL_RB2,
+ BD72720_REG_BUCK1_VSEL_RB3,
+
+ BD72720_REG_BUCK2_ON,
+ BD72720_REG_BUCK2_MODE,
+ BD72720_REG_BUCK2_VSEL_DI,
+ BD72720_REG_BUCK2_VSEL_I,
+ BD72720_REG_BUCK2_VSEL_S,
+ /* Run vsel */
+ BD72720_REG_BUCK2_VSEL_R,
+
+ BD72720_REG_BUCK3_ON,
+ BD72720_REG_BUCK3_MODE,
+ BD72720_REG_BUCK3_VSEL_DI,
+ BD72720_REG_BUCK3_VSEL_I,
+ BD72720_REG_BUCK3_VSEL_S,
+ BD72720_REG_BUCK3_VSEL_R,
+
+ BD72720_REG_BUCK4_ON,
+ BD72720_REG_BUCK4_MODE,
+ BD72720_REG_BUCK4_VSEL_DI,
+ BD72720_REG_BUCK4_VSEL_I,
+ BD72720_REG_BUCK4_VSEL_S,
+ BD72720_REG_BUCK4_VSEL_R,
+
+ BD72720_REG_BUCK5_ON,
+ BD72720_REG_BUCK5_MODE,
+ BD72720_REG_BUCK5_VSEL,
+
+ BD72720_REG_BUCK6_ON,
+ BD72720_REG_BUCK6_MODE,
+ BD72720_REG_BUCK6_VSEL,
+
+ BD72720_REG_BUCK7_ON,
+ BD72720_REG_BUCK7_MODE,
+ BD72720_REG_BUCK7_VSEL,
+
+ BD72720_REG_BUCK8_ON,
+ BD72720_REG_BUCK8_MODE,
+ BD72720_REG_BUCK8_VSEL,
+
+ BD72720_REG_BUCK9_ON,
+ BD72720_REG_BUCK9_MODE,
+ BD72720_REG_BUCK9_VSEL,
+
+ BD72720_REG_BUCK10_ON,
+ BD72720_REG_BUCK10_MODE,
+ BD72720_REG_BUCK10_VSEL,
+
+ BD72720_REG_LDO1_ON,
+ BD72720_REG_LDO1_MODE1,
+ BD72720_REG_LDO1_MODE2,
+ BD72720_REG_LDO1_VSEL_DI,
+ BD72720_REG_LDO1_VSEL_I,
+ BD72720_REG_LDO1_VSEL_S,
+ BD72720_REG_LDO1_VSEL_RB,
+ BD72720_REG_LDO1_VSEL_R0,
+ BD72720_REG_LDO1_VSEL_R1,
+ BD72720_REG_LDO1_VSEL_R2,
+ BD72720_REG_LDO1_VSEL_R3,
+
+ BD72720_REG_LDO2_ON,
+ BD72720_REG_LDO2_MODE,
+ BD72720_REG_LDO2_VSEL_DI,
+ BD72720_REG_LDO2_VSEL_I,
+ BD72720_REG_LDO2_VSEL_S,
+ BD72720_REG_LDO2_VSEL_R,
+
+ BD72720_REG_LDO3_ON,
+ BD72720_REG_LDO3_MODE,
+ BD72720_REG_LDO3_VSEL_DI,
+ BD72720_REG_LDO3_VSEL_I,
+ BD72720_REG_LDO3_VSEL_S,
+ BD72720_REG_LDO3_VSEL_R,
+
+ BD72720_REG_LDO4_ON,
+ BD72720_REG_LDO4_MODE,
+ BD72720_REG_LDO4_VSEL_DI,
+ BD72720_REG_LDO4_VSEL_I,
+ BD72720_REG_LDO4_VSEL_S,
+ BD72720_REG_LDO4_VSEL_R,
+
+ BD72720_REG_LDO5_ON,
+ BD72720_REG_LDO5_MODE,
+ BD72720_REG_LDO5_VSEL,
+
+ BD72720_REG_LDO6_ON,
+ BD72720_REG_LDO6_MODE,
+ BD72720_REG_LDO6_VSEL,
+
+ BD72720_REG_LDO7_ON,
+ BD72720_REG_LDO7_MODE,
+ BD72720_REG_LDO7_VSEL,
+
+ BD72720_REG_LDO8_ON,
+ BD72720_REG_LDO8_MODE,
+ BD72720_REG_LDO8_VSEL,
+
+ BD72720_REG_LDO9_ON,
+ BD72720_REG_LDO9_MODE,
+ BD72720_REG_LDO9_VSEL,
+
+ BD72720_REG_LDO10_ON,
+ BD72720_REG_LDO10_MODE,
+ BD72720_REG_LDO10_VSEL,
+
+ BD72720_REG_LDO11_ON,
+ BD72720_REG_LDO11_MODE,
+ BD72720_REG_LDO11_VSEL,
+
+ BD72720_REG_GPIO1_ON = 0x8b,
+ BD72720_REG_GPIO2_ON,
+ BD72720_REG_GPIO3_ON,
+ BD72720_REG_GPIO4_ON,
+ BD72720_REG_GPIO5_ON,
+
+ BD72720_REG_GPIO1_CTRL,
+ BD72720_REG_GPIO2_CTRL,
+#define BD72720_GPIO_IRQ_TYPE_MASK GENMASK(6, 4)
+#define BD72720_GPIO_IRQ_TYPE_FALLING 0x0
+#define BD72720_GPIO_IRQ_TYPE_RISING 0x1
+#define BD72720_GPIO_IRQ_TYPE_BOTH 0x2
+#define BD72720_GPIO_IRQ_TYPE_HIGH 0x3
+#define BD72720_GPIO_IRQ_TYPE_LOW 0x4
+ BD72720_REG_GPIO3_CTRL,
+ BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL,
+#define BD72720_GPIO_DRIVE_MASK BIT(1)
+#define BD72720_GPIO_HIGH BIT(0)
+
+ BD72720_REG_EPDEN_CTRL,
+ BD72720_REG_GATECNT_CTRL,
+ BD72720_REG_LED_CTRL,
+
+ BD72720_REG_PWRON_CFG1,
+ BD72720_REG_PWRON_CFG2,
+
+ BD72720_REG_OUT32K,
+ BD72720_REG_CONF,
+ BD72720_REG_HALL_STAT,
+
+ BD72720_REG_RTC_SEC = 0xa0,
+#define BD72720_REG_RTC_START BD72720_REG_RTC_SEC
+ BD72720_REG_RTC_MIN,
+ BD72720_REG_RTC_HOUR,
+ BD72720_REG_RTC_WEEK,
+ BD72720_REG_RTC_DAY,
+ BD72720_REG_RTC_MON,
+ BD72720_REG_RTC_YEAR,
+
+ BD72720_REG_RTC_ALM0_SEC,
+#define BD72720_REG_RTC_ALM_START BD72720_REG_RTC_ALM0_SEC
+ BD72720_REG_RTC_ALM0_MIN,
+ BD72720_REG_RTC_ALM0_HOUR,
+ BD72720_REG_RTC_ALM0_WEEK,
+ BD72720_REG_RTC_ALM0_MON,
+ BD72720_REG_RTC_ALM0_YEAR,
+
+ BD72720_REG_RTC_ALM1_SEC,
+ BD72720_REG_RTC_ALM1_MIN,
+ BD72720_REG_RTC_ALM1_HOUR,
+ BD72720_REG_RTC_ALM1_WEEK,
+ BD72720_REG_RTC_ALM1_MON,
+ BD72720_REG_RTC_ALM1_YEAR,
+
+ BD72720_REG_RTC_ALM0_EN,
+ BD72720_REG_RTC_ALM1_EN,
+ BD72720_REG_RTC_ALM2,
+
+ BD72720_REG_INT_LVL1_EN = 0xc0,
+#define BD72720_MASK_LVL1_EN_ALL GENMASK(7, 0)
+ BD72720_REG_INT_PS1_EN,
+ BD72720_REG_INT_PS2_EN,
+ BD72720_REG_INT_DVS1_EN,
+ BD72720_REG_INT_DVS2_EN,
+ BD72720_REG_INT_VBUS_EN,
+ BD72720_REG_INT_VSYS_EN,
+ BD72720_REG_INT_CHG_EN,
+ BD72720_REG_INT_BAT1_EN,
+ BD72720_REG_INT_BAT2_EN,
+ BD72720_REG_INT_IBAT_EN,
+ BD72720_REG_INT_ETC1_EN,
+ BD72720_REG_INT_ETC2_EN,
+
+ /*
+ * The _STAT registers inform IRQ line state, and are used to ack IRQ.
+ * The _SRC registers below indicate current state of the function
+ * connected to the line.
+ */
+ BD72720_REG_INT_LVL1_STAT,
+ BD72720_REG_INT_PS1_STAT,
+ BD72720_REG_INT_PS2_STAT,
+ BD72720_REG_INT_DVS1_STAT,
+ BD72720_REG_INT_DVS2_STAT,
+ BD72720_REG_INT_VBUS_STAT,
+ BD72720_REG_INT_VSYS_STAT,
+ BD72720_REG_INT_CHG_STAT,
+ BD72720_REG_INT_BAT1_STAT,
+ BD72720_REG_INT_BAT2_STAT,
+ BD72720_REG_INT_IBAT_STAT,
+ BD72720_REG_INT_ETC1_STAT,
+ BD72720_REG_INT_ETC2_STAT,
+
+ BD72720_REG_INT_LVL1_SRC,
+ BD72720_REG_INT_PS1_SRC,
+ BD72720_REG_INT_PS2_SRC,
+ BD72720_REG_INT_DVS1_SRC,
+ BD72720_REG_INT_DVS2_SRC,
+ BD72720_REG_INT_VBUS_SRC,
+#define BD72720_MASK_DCIN_DET BIT(1)
+ BD72720_REG_INT_VSYS_SRC,
+ BD72720_REG_INT_CHG_SRC,
+ BD72720_REG_INT_BAT1_SRC,
+ BD72720_REG_INT_BAT2_SRC,
+ BD72720_REG_INT_IBAT_SRC,
+ BD72720_REG_INT_ETC1_SRC,
+ BD72720_REG_INT_ETC2_SRC,
+};
+
+/* Register masks */
+#define BD72720_MASK_DEEP_IDLE_EN BIT(0)
+#define BD72720_MASK_IDLE_EN BIT(1)
+#define BD72720_MASK_SUSPEND_EN BIT(2)
+#define BD72720_MASK_RUN_B_EN BIT(3)
+#define BD72720_MASK_RUN_0_EN BIT(4)
+#define BD72720_MASK_RUN_1_EN BIT(5)
+#define BD72720_MASK_RUN_2_EN BIT(6)
+#define BD72720_MASK_RUN_3_EN BIT(7)
+
+#define BD72720_MASK_RAMP_UP_DELAY GENMASK(7, 6)
+#define BD72720_MASK_BUCK_VSEL GENMASK(7, 0)
+#define BD72720_MASK_LDO12346_VSEL GENMASK(6, 0)
+#define BD72720_MASK_LDO_VSEL GENMASK(7, 0)
+
+#define BD72720_I2C4C_ADDR_OFFSET 0x100
+
+/* Registers behind I2C slave 0x4c */
+enum {
+ BD72720_REG_CHG_STATE = BD72720_I2C4C_ADDR_OFFSET,
+ BD72720_REG_CHG_LAST_STATE,
+ BD72720_REG_CHG_VBUS_STAT,
+ BD72720_REG_CHG_VSYS_STAT,
+ BD72720_REG_CHG_BAT_TEMP_STAT,
+ BD72720_REG_CHG_WDT_STAT,
+ BD72720_REG_CHG_ILIM_STAT,
+ BD72720_REG_CHG_CHG_STAT,
+ BD72720_REG_CHG_EN,
+ BD72720_REG_CHG_INIT,
+ BD72720_REG_CHG_CTRL,
+ BD72720_REG_CHG_SET_1,
+ BD72720_REG_CHG_SET_2,
+ BD72720_REG_CHG_SET_3,
+ BD72720_REG_CHG_VPRE,
+ BD72720_REG_CHG_VBAT_1,
+ BD72720_REG_CHG_VBAT_2,
+ BD72720_REG_CHG_VBAT_3,
+ BD72720_REG_CHG_VBAT_4,
+ BD72720_REG_CHG_BAT_SET_1,
+ BD72720_REG_CHG_BAT_SET_2,
+ BD72720_REG_CHG_BAT_SET_3,
+ BD72720_REG_CHG_IPRE,
+ BD72720_REG_CHG_IFST_TERM,
+ BD72720_REG_CHG_VSYS_REG,
+ BD72720_REG_CHG_VBUS_SET,
+ BD72720_REG_CHG_WDT_PRE,
+ BD72720_REG_CHG_WDT_FST,
+ BD72720_REG_CHG_LED_CTRL,
+ BD72720_REG_CHG_CFG_1,
+ BD72720_REG_CHG_IFST_1,
+ BD72720_REG_CHG_IFST_2,
+ BD72720_REG_CHG_IFST_3,
+ BD72720_REG_CHG_IFST_4,
+ BD72720_REG_CHG_S_CFG_1,
+ BD72720_REG_CHG_S_CFG_2,
+ BD72720_REG_RS_VBUS,
+ BD72720_REG_RS_IBUS,
+ BD72720_REG_RS_VSYS,
+ BD72720_REG_VSYS_STATE_STAT, /* 0x27 + offset*/
+
+ BD72720_REG_VM_VBAT_U = BD72720_I2C4C_ADDR_OFFSET + 0x30,
+ BD72720_REG_VM_VBAT_L,
+ BD72720_REG_VM_OCV_PRE_U,
+ BD72720_REG_VM_OCV_PRE_L,
+ BD72720_REG_VM_OCV_PST_U,
+ BD72720_REG_VM_OCV_PST_L,
+ BD72720_REG_VM_OCV_PWRON_U,
+ BD72720_REG_VM_OCV_PWRON_L,
+ BD72720_REG_VM_DVBAT_IMP_U,
+ BD72720_REG_VM_DVBAT_IMP_L,
+ BD72720_REG_VM_SA_VBAT_U,
+ BD72720_REG_VM_SA_VBAT_L,
+ BD72720_REG_VM_SA_VBAT_MIN_U,
+ BD72720_REG_VM_SA_VBAT_MIN_L,
+ BD72720_REG_VM_SA_VBAT_MAX_U,
+ BD72720_REG_VM_SA_VBAT_MAX_L,
+ BD72720_REG_REX_SA_VBAT_U,
+ BD72720_REG_REX_SA_VBAT_L,
+ BD72720_REG_VM_VSYS_U,
+ BD72720_REG_VM_VSYS_L,
+ BD72720_REG_VM_SA_VSYS_U,
+ BD72720_REG_VM_SA_VSYS_L,
+ BD72720_REG_VM_SA_VSYS_MIN_U,
+ BD72720_REG_VM_SA_VSYS_MIN_L,
+ BD72720_REG_VM_SA_VSYS_MAX_U,
+ BD72720_REG_VM_SA_VSYS_MAX_L,
+ BD72720_REG_VM_SA2_VSYS_U,
+ BD72720_REG_VM_SA2_VSYS_L,
+ BD72720_REG_VM_VBUS_U,
+#define BD72720_MASK_VDCIN_U GENMASK(3, 0)
+ BD72720_REG_VM_VBUS_L,
+ BD72720_REG_VM_BATID_U,
+ BD72720_REG_VM_BATID_L,
+ BD72720_REG_VM_BATID_NOLOAD_U,
+ BD72720_REG_VM_BATID_NOLOAD_L,
+ BD72720_REG_VM_BATID_OFS_U,
+ BD72720_REG_VM_BATID_OFS_L,
+ BD72720_REG_VM_VTH_U,
+ BD72720_REG_VM_VTH_L,
+ BD72720_REG_VM_VTH_CORR_U,
+ BD72720_REG_VM_VTH_CORR_L,
+ BD72720_REG_VM_BTMP_U,
+ BD72720_REG_VM_BTMP_L,
+ BD72720_REG_VM_BTMP_IMP_U,
+ BD72720_REG_VM_BTMP_IMP_L,
+ BD72720_REG_VM_VF_U,
+ BD72720_REG_VM_VF_L,
+ BD72720_REG_VM_BATID_TH_U,
+ BD72720_REG_VM_BATID_TH_L,
+ BD72720_REG_VM_BTMP_OV_THR,
+ BD72720_REG_VM_BTMP_OV_DUR,
+ BD72720_REG_VM_BTMP_LO_THR,
+ BD72720_REG_VM_BTMP_LO_DUR,
+ BD72720_REG_ALM_VBAT_TH_U,
+ BD72720_REG_ALM_VBAT_TH_L,
+ BD72720_REG_ALM_VSYS_TH,
+ BD72720_REG_ALM_VBUS_TH,
+ BD72720_REG_ALM_VF_TH,
+ BD72720_REG_VSYS_MAX,
+ BD72720_REG_VSYS_MIN,
+ BD72720_REG_VM_VSYS_SA_MINMAX_CTRL,
+ BD72720_REG_VM_SA_CFG, /* 0x6c + offset*/
+
+ BD72720_REG_CC_CURCD_U = BD72720_I2C4C_ADDR_OFFSET + 0x70,
+ BD72720_REG_CC_CURCD_L,
+ BD72720_REG_CC_CURCD_IMP_U,
+ BD72720_REG_CC_CURCD_IMP_L,
+ BD72720_REG_CC_SA_CURCD_U,
+ BD72720_REG_CC_SA_CURCD_L,
+ BD72720_REG_CC_OCUR_MON,
+ BD72720_REG_CC_CCNTD_3,
+ BD72720_REG_CC_CCNTD_2,
+ BD72720_REG_CC_CCNTD_1,
+ BD72720_REG_CC_CCNTD_0,
+ BD72720_REG_REX_CCNTD_3,
+ BD72720_REG_REX_CCNTD_2,
+ BD72720_REG_REX_CCNTD_1,
+ BD72720_REG_REX_CCNTD_0,
+ BD72720_REG_FULL_CCNTD_3,
+ BD72720_REG_FULL_CCNTD_2,
+ BD72720_REG_FULL_CCNTD_1,
+ BD72720_REG_FULL_CCNTD_0,
+ BD72720_REG_CCNTD_CHG_3,
+ BD72720_REG_CCNTD_CHG_2,
+ BD72720_REG_CC_STAT,
+ BD72720_REG_CC_CTRL,
+ BD72720_REG_CC_OCUR_THR_1,
+ BD72720_REG_CC_OCUR_THR_2,
+ BD72720_REG_CC_OCUR_THR_3,
+ BD72720_REG_REX_CURCD_TH,
+ BD72720_REG_CC_BATCAP1_TH_U,
+ BD72720_REG_CC_BATCAP1_TH_L,
+ BD72720_REG_CC_BATCAP2_TH_U,
+ BD72720_REG_CC_BATCAP2_TH_L,
+ BD72720_REG_CC_BATCAP3_TH_U,
+ BD72720_REG_CC_BATCAP3_TH_L,
+ BD72720_REG_CC_CCNTD_CTRL,
+ BD72720_REG_CC_SA_CFG, /* 0x92 + offset*/
+ BD72720_REG_IMPCHK_CTRL = BD72720_I2C4C_ADDR_OFFSET + 0xa0,
+};
+
+#endif /* __LINUX_MFD_BD72720_H */
diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h
index 579e8dcfcca4..0a284919a6c3 100644
--- a/include/linux/mfd/rohm-generic.h
+++ b/include/linux/mfd/rohm-generic.h
@@ -16,6 +16,7 @@ enum rohm_chip_type {
ROHM_CHIP_TYPE_BD71828,
ROHM_CHIP_TYPE_BD71837,
ROHM_CHIP_TYPE_BD71847,
+ ROHM_CHIP_TYPE_BD72720,
ROHM_CHIP_TYPE_BD96801,
ROHM_CHIP_TYPE_BD96802,
ROHM_CHIP_TYPE_BD96805,
--
2.51.1
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v5 09/16] regulator: bd71828: rename IC specific entities
From: Matti Vaittinen @ 2025-11-20 8:23 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 5360 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The new ROHM BD72720 PMIC has similarities with the BD71828. It makes
sense to support the regulator control for both PMICs using the same
driver. It is often more clear to have the IC specific functions and
globals named starting with the chip-name. So, as a preparatory step,
prefix the BD71828 specific functions and globals with the bd71828.
It would be tempting to try also removing the chip ID from those
functions which will be common for both PMICs. I have bad experiences on
this as it tends to lead to problems when yet another IC is being
supported with the same driver, and we will have some functions used for
all, some for two of the three, and some for just one. At this point
I used to start inventing wildcards like BD718XX or BD7272X. This
approach is pretty much always failing as we tend to eventually have
something like BD73900 - where all the wildcard stuff will break down.
So, my approach these days is to:
- keep the original chip-id prefix for anything that had it already
(and avoid the churn).
- use same prefix for all things that are used by multiple ICs -
typically the chip-ID of the first chip. This typically matches also
the driver and file names.
- use specific chip-ID as a prefix for anything which is specific to
just one chip.
As a preparatory step to adding the BD72720, add bd71828 prefix to all
commonly usable functions and globals.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Mark Brown <broonie@kernel.org>
---
Revision history:
RFCv1 =>:
- No changes
No functional changes intended.
---
drivers/regulator/bd71828-regulator.c | 32 +++++++++++++--------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/regulator/bd71828-regulator.c b/drivers/regulator/bd71828-regulator.c
index dd871ffe979c..3d18dbfdb84e 100644
--- a/drivers/regulator/bd71828-regulator.c
+++ b/drivers/regulator/bd71828-regulator.c
@@ -28,7 +28,7 @@ struct bd71828_regulator_data {
int reg_init_amnt;
};
-static const struct reg_init buck1_inits[] = {
+static const struct reg_init bd71828_buck1_inits[] = {
/*
* DVS Buck voltages can be changed by register values or via GPIO.
* Use register accesses by default.
@@ -40,7 +40,7 @@ static const struct reg_init buck1_inits[] = {
},
};
-static const struct reg_init buck2_inits[] = {
+static const struct reg_init bd71828_buck2_inits[] = {
{
.reg = BD71828_REG_PS_CTRL_1,
.mask = BD71828_MASK_DVS_BUCK2_CTRL,
@@ -48,7 +48,7 @@ static const struct reg_init buck2_inits[] = {
},
};
-static const struct reg_init buck6_inits[] = {
+static const struct reg_init bd71828_buck6_inits[] = {
{
.reg = BD71828_REG_PS_CTRL_1,
.mask = BD71828_MASK_DVS_BUCK6_CTRL,
@@ -56,7 +56,7 @@ static const struct reg_init buck6_inits[] = {
},
};
-static const struct reg_init buck7_inits[] = {
+static const struct reg_init bd71828_buck7_inits[] = {
{
.reg = BD71828_REG_PS_CTRL_1,
.mask = BD71828_MASK_DVS_BUCK7_CTRL,
@@ -102,9 +102,9 @@ static int buck_set_hw_dvs_levels(struct device_node *np,
return rohm_regulator_set_dvs_levels(&data->dvs, np, desc, cfg->regmap);
}
-static int ldo6_parse_dt(struct device_node *np,
- const struct regulator_desc *desc,
- struct regulator_config *cfg)
+static int bd71828_ldo6_parse_dt(struct device_node *np,
+ const struct regulator_desc *desc,
+ struct regulator_config *cfg)
{
int ret, i;
uint32_t uv = 0;
@@ -212,8 +212,8 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
*/
.lpsr_on_mask = BD71828_MASK_LPSR_EN,
},
- .reg_inits = buck1_inits,
- .reg_init_amnt = ARRAY_SIZE(buck1_inits),
+ .reg_inits = bd71828_buck1_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd71828_buck1_inits),
},
{
.desc = {
@@ -253,8 +253,8 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
.lpsr_reg = BD71828_REG_BUCK2_SUSP_VOLT,
.lpsr_mask = BD71828_MASK_BUCK1267_VOLT,
},
- .reg_inits = buck2_inits,
- .reg_init_amnt = ARRAY_SIZE(buck2_inits),
+ .reg_inits = bd71828_buck2_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd71828_buck2_inits),
},
{
.desc = {
@@ -399,8 +399,8 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
.lpsr_reg = BD71828_REG_BUCK6_SUSP_VOLT,
.lpsr_mask = BD71828_MASK_BUCK1267_VOLT,
},
- .reg_inits = buck6_inits,
- .reg_init_amnt = ARRAY_SIZE(buck6_inits),
+ .reg_inits = bd71828_buck6_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd71828_buck6_inits),
},
{
.desc = {
@@ -440,8 +440,8 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
.lpsr_reg = BD71828_REG_BUCK7_SUSP_VOLT,
.lpsr_mask = BD71828_MASK_BUCK1267_VOLT,
},
- .reg_inits = buck7_inits,
- .reg_init_amnt = ARRAY_SIZE(buck7_inits),
+ .reg_inits = bd71828_buck7_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd71828_buck7_inits),
},
{
.desc = {
@@ -633,7 +633,7 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
* LDO6 only supports enable/disable for all states.
* Voltage for LDO6 is fixed.
*/
- .of_parse_cb = ldo6_parse_dt,
+ .of_parse_cb = bd71828_ldo6_parse_dt,
},
}, {
.desc = {
--
2.51.1
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v5 10/16] regulator: bd71828: Support ROHM BD72720
From: Matti Vaittinen @ 2025-11-20 8:23 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 40951 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
ROHM BD72720 is a power management IC which integrates 10 buck and 11 LDO
regulators. This PMIC has plenty of commonalities with the BD71828 and
BD71879.
The BD72720 does also have similar 'run-level'-concept as the BD71828 had.
It allows controlling the regulator's 'en masse', although only BUCK1
and LDO1 can utilize this in BD72720. Similar to BD71828, this 'en
masse' -control is not supported by this driver.
Support the voltage and enable/disable state control for the BD72720.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
---
Revision history:
v3 =>:
- No changes
v2 => v3:
- The ldon-head dt-property was changed to microvolts. Adapt the driver
to that
RFCv1 => v2:
- No changes
There are some new variants planned. Most notably, the BD73900 should be
similar to the BD72720 what comes to the regulator control logic.
If the run-level control is needed, there are some downstream extensions
available at:
https://rohmsemiconductor.github.io/Linux-Kernel-PMIC-Drivers/BD72720/
---
drivers/regulator/Kconfig | 8 +-
drivers/regulator/bd71828-regulator.c | 993 +++++++++++++++++++++++++-
2 files changed, 992 insertions(+), 9 deletions(-)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index d84f3d054c59..660863f096e3 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -241,13 +241,13 @@ config REGULATOR_BD71815
will be called bd71815-regulator.
config REGULATOR_BD71828
- tristate "ROHM BD71828 Power Regulator"
+ tristate "ROHM BD71828, BD72720 and BD73900 Power Regulators"
depends on MFD_ROHM_BD71828
select REGULATOR_ROHM
help
- This driver supports voltage regulators on ROHM BD71828 PMIC.
- This will enable support for the software controllable buck
- and LDO regulators.
+ This driver supports voltage regulators on ROHM BD71828,
+ BD71879, BD72720 and BD73900 PMICs. This will enable
+ support for the software controllable buck and LDO regulators.
This driver can also be built as a module. If so, the module
will be called bd71828-regulator.
diff --git a/drivers/regulator/bd71828-regulator.c b/drivers/regulator/bd71828-regulator.c
index 3d18dbfdb84e..ba16671ece42 100644
--- a/drivers/regulator/bd71828-regulator.c
+++ b/drivers/regulator/bd71828-regulator.c
@@ -3,12 +3,15 @@
// bd71828-regulator.c ROHM BD71828GW-DS1 regulator driver
//
+#include <linux/cleanup.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/rohm-bd71828.h>
+#include <linux/mfd/rohm-bd72720.h>
#include <linux/module.h>
+#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -16,6 +19,7 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
+#define BD72720_MASK_LDON_HEAD GENMASK(2, 0)
struct reg_init {
unsigned int reg;
unsigned int mask;
@@ -64,6 +68,26 @@ static const struct reg_init bd71828_buck7_inits[] = {
},
};
+#define BD72720_MASK_DVS_BUCK1_CTRL BIT(4)
+#define BD72720_MASK_DVS_LDO1_CTRL BIT(5)
+
+static const struct reg_init bd72720_buck1_inits[] = {
+ {
+ .reg = BD72720_REG_PS_CTRL_2,
+ .mask = BD72720_MASK_DVS_BUCK1_CTRL,
+ .val = 0, /* Disable "run-level" control */
+ },
+};
+
+static const struct reg_init bd72720_ldo1_inits[] = {
+ {
+ .reg = BD72720_REG_PS_CTRL_2,
+ .mask = BD72720_MASK_DVS_LDO1_CTRL,
+ .val = 0, /* Disable "run-level" control */
+ },
+};
+
+/* BD71828 Buck voltages */
static const struct linear_range bd71828_buck1267_volts[] = {
REGULATOR_LINEAR_RANGE(500000, 0x00, 0xef, 6250),
REGULATOR_LINEAR_RANGE(2000000, 0xf0, 0xff, 0),
@@ -84,13 +108,79 @@ static const struct linear_range bd71828_buck5_volts[] = {
REGULATOR_LINEAR_RANGE(3300000, 0x10, 0x1f, 0),
};
+/* BD71828 LDO voltages */
static const struct linear_range bd71828_ldo_volts[] = {
REGULATOR_LINEAR_RANGE(800000, 0x00, 0x31, 50000),
REGULATOR_LINEAR_RANGE(3300000, 0x32, 0x3f, 0),
};
+/* BD72720 Buck voltages */
+static const struct linear_range bd72720_buck1234_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0xc0, 6250),
+ REGULATOR_LINEAR_RANGE(1700000, 0xc1, 0xff, 0),
+};
+
+static const struct linear_range bd72720_buck589_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0x78, 10000),
+ REGULATOR_LINEAR_RANGE(1700000, 0x79, 0xff, 0),
+};
+
+static const struct linear_range bd72720_buck67_volts[] = {
+ REGULATOR_LINEAR_RANGE(1500000, 0x00, 0xb4, 10000),
+ REGULATOR_LINEAR_RANGE(3300000, 0xb5, 0xff, 0),
+};
+
+/*
+ * The BUCK10 on BD72720 has two modes of operation, depending on a LDON_HEAD
+ * setting. When LDON_HEAD is 0x0, the behaviour is as with other bucks, eg.
+ * voltage can be set to a values indicated below using the VSEL register.
+ *
+ * However, when LDON_HEAD is set to 0x1 ... 0x7, BUCK 10 voltage is, according
+ * to the data-sheet, "automatically adjusted following LDON_HEAD setting and
+ * clamped to BUCK10_VID setting".
+ *
+ * Again, reading the data-sheet shows a "typical connection" where the BUCK10
+ * is used to supply the LDOs 1-4. My assumption is that in practice, this
+ * means that the BUCK10 voltage will be adjusted based on the maximum output
+ * of the LDO 1-4 (to minimize power loss). This makes sense.
+ *
+ * Auto-adjusting regulators aren't something I really like to model in the
+ * driver though - and, if the auto-adjustment works as intended, then there
+ * should really be no need to software to care about the buck10 voltages.
+ * If enable/disable control is still needed, we can implement buck10 as a
+ * regulator with only the enable/disable ops - and device-tree can be used
+ * to model the supply-relations. I believe this could allow the regulator
+ * framework to automagically disable the BUCK10 if all LDOs that are being
+ * supplied by it are disabled.
+ */
+static const struct linear_range bd72720_buck10_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0xc0, 6250),
+ REGULATOR_LINEAR_RANGE(1700000, 0xc1, 0xff, 0),
+};
+
+/* BD72720 LDO voltages */
+static const struct linear_range bd72720_ldo1234_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0x50, 6250),
+ REGULATOR_LINEAR_RANGE(1000000, 0x51, 0x7f, 0),
+};
+
+static const struct linear_range bd72720_ldo57891011_volts[] = {
+ REGULATOR_LINEAR_RANGE(750000, 0x00, 0xff, 10000),
+};
+
+static const struct linear_range bd72720_ldo6_volts[] = {
+ REGULATOR_LINEAR_RANGE(600000, 0x00, 0x78, 10000),
+ REGULATOR_LINEAR_RANGE(1800000, 0x79, 0x7f, 0),
+};
+
static const unsigned int bd71828_ramp_delay[] = { 2500, 5000, 10000, 20000 };
+/*
+ * BD72720 supports setting both the ramp-up and ramp-down values
+ * separately. Do we need to support ramp-down setting?
+ */
+static const unsigned int bd72720_ramp_delay[] = { 5000, 7500, 10000, 12500 };
+
static int buck_set_hw_dvs_levels(struct device_node *np,
const struct regulator_desc *desc,
struct regulator_config *cfg)
@@ -171,6 +261,24 @@ static const struct regulator_ops bd71828_ldo6_ops = {
.is_enabled = regulator_is_enabled_regmap,
};
+static const struct regulator_ops bd72720_regulator_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
+};
+
+static const struct regulator_ops bd72720_buck10_ldon_head_op = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
+};
+
static const struct bd71828_regulator_data bd71828_rdata[] = {
{
.desc = {
@@ -677,22 +785,890 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
},
};
+#define BD72720_BUCK10_DESC_INDEX 10
+#define BD72720_NUM_BUCK_VOLTS 0x100
+#define BD72720_NUM_LDO_VOLTS 0x100
+#define BD72720_NUM_LDO12346_VOLTS 0x80
+
+static const struct bd71828_regulator_data bd72720_rdata[] = {
+ {
+ .desc = {
+ .name = "buck1",
+ .of_match = of_match_ptr("buck1"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK1,
+ .type = REGULATOR_VOLTAGE,
+
+ /*
+ * The BD72720 BUCK1 and LDO1 support GPIO toggled
+ * sub-RUN states called RUN0, RUN1, RUN2 and RUN3.
+ * The "operating mode" (sub-RUN states or normal)
+ * can be changed by a register.
+ *
+ * When the sub-RUN states are used, the voltage and
+ * enable state depend on a state specific
+ * configuration. The voltage and enable configuration
+ * for BUCK1 and LDO1 can be defined for each sub-RUN
+ * state using BD72720_REG_[BUCK,LDO]1_VSEL_R[0,1,2,3]
+ * voltage selection registers and the bits
+ * BD72720_MASK_RUN_[0,1,2,3]_EN in the enable registers.
+ * The PMIC will change both the BUCK1 and LDO1 voltages
+ * to the states defined in these registers when
+ * "DVS GPIOs" are toggled.
+ *
+ * If RUN 0 .. RUN 4 states are to be used, the normal
+ * voltage configuration mechanisms do not apply
+ * and we should overwrite the ops and ignore the
+ * voltage setting/getting registers which are setup
+ * here. This is not supported for now. If you need
+ * this functionality, you may try merging functionality
+ * from a downstream driver:
+ * https://rohmsemiconductor.github.io/Linux-Kernel-PMIC-Drivers/BD72720/
+ */
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK1_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK1_VSEL_RB,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK1_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR, /* Deep idle in data-sheet */
+ .run_reg = BD72720_REG_BUCK1_VSEL_RB,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK1_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK1_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK1_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ .reg_inits = bd72720_buck1_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd72720_buck1_inits),
+ }, {
+ .desc = {
+ .name = "buck2",
+ .of_match = of_match_ptr("buck2"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK2,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK2_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK2_VSEL_R,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK2_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK2_VSEL_R,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK2_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK2_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK2_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck3",
+ .of_match = of_match_ptr("buck3"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK3,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK3_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK3_VSEL_R,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK3_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK3_VSEL_R,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK3_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK3_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK3_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck4",
+ .of_match = of_match_ptr("buck4"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK4,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK4_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK4_VSEL_R,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK4_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK4_VSEL_R,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK4_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK4_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK4_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck5",
+ .of_match = of_match_ptr("buck5"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK5,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck589_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK5_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK5_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK5_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK5_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck6",
+ .of_match = of_match_ptr("buck6"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK6,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck67_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck67_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK6_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK6_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK6_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK6_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck7",
+ .of_match = of_match_ptr("buck7"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK7,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck67_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck67_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK7_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK7_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK7_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK7_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck8",
+ .of_match = of_match_ptr("buck8"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK8,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck589_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK8_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK8_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK8_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK8_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck9",
+ .of_match = of_match_ptr("buck9"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK9,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck589_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK9_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK9_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK9_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK9_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck10",
+ .of_match = of_match_ptr("buck10"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK10,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck10_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck10_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK10_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK10_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK10_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK10_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo1",
+ .of_match = of_match_ptr("ldo1"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO1,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO1_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO1_VSEL_RB,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO1_MODE1,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO1_VSEL_RB,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO1_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO1_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO1_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ .reg_inits = bd72720_ldo1_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd72720_ldo1_inits),
+ }, {
+ .desc = {
+ .name = "ldo2",
+ .of_match = of_match_ptr("ldo2"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO2,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO2_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO2_VSEL_R,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO2_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO2_VSEL_R,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO2_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO2_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO2_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo3",
+ .of_match = of_match_ptr("ldo3"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO3,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO3_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO3_VSEL_R,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO3_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO3_VSEL_R,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO3_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO3_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO3_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo4",
+ .of_match = of_match_ptr("ldo4"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO4,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO4_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO4_VSEL_R,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO4_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO4_VSEL_R,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO4_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO4_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO4_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo5",
+ .of_match = of_match_ptr("ldo5"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO5,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO5_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO5_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO5_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO5_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo6",
+ .of_match = of_match_ptr("ldo6"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO6,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo6_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo6_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO6_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO6_VSEL,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO6_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO6_VSEL,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo7",
+ .of_match = of_match_ptr("ldo7"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO7,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO7_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO7_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO7_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO7_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo8",
+ .of_match = of_match_ptr("ldo8"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO8,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO8_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO8_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO8_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO8_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo9",
+ .of_match = of_match_ptr("ldo9"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO9,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO9_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO9_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO9_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO9_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo10",
+ .of_match = of_match_ptr("ldo10"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO10,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO10_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO10_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO10_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO10_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo11",
+ .of_match = of_match_ptr("ldo11"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO11,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO11_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO11_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO11_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO11_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ },
+};
+
+static int bd72720_buck10_ldon_head_mode(struct device *dev,
+ struct device_node *npreg,
+ struct regmap *regmap,
+ struct regulator_desc *buck10_desc)
+{
+ struct device_node *np __free(device_node) =
+ of_get_child_by_name(npreg, "buck10");
+ uint32_t ldon_head;
+ int ldon_val;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "failed to find buck10 regulator node\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_read_u32(np, "rohm,ldon-head-microvolt", &ldon_head);
+ if (ret == -EINVAL)
+ return 0;
+ if (ret)
+ return ret;
+
+ /*
+ * LDON_HEAD mode means the BUCK10 is used to supply LDOs 1-4 and
+ * the BUCK 10 voltage is automatically set to follow LDO 1-4
+ * settings. Thus the BUCK10 should not allow voltage [g/s]etting.
+ */
+ buck10_desc->ops = &bd72720_buck10_ldon_head_op;
+
+ ldon_val = ldon_head / 50000 + 1;
+ if (ldon_head > 300000) {
+ dev_warn(dev, "Unsupported LDON_HEAD, clamping to 300 mV\n");
+ ldon_val = 7;
+ }
+
+ return regmap_update_bits(regmap, BD72720_REG_LDO1_MODE2,
+ BD72720_MASK_LDON_HEAD, ldon_val);
+}
+
+static int bd72720_dt_parse(struct device *dev,
+ struct regulator_desc *buck10_desc,
+ struct regmap *regmap)
+{
+ struct device_node *nproot __free(device_node) =
+ of_get_child_by_name(dev->parent->of_node, "regulators");
+
+ if (!nproot) {
+ dev_err(dev, "failed to find regulators node\n");
+ return -ENODEV;
+ }
+
+ return bd72720_buck10_ldon_head_mode(dev, nproot, regmap, buck10_desc);
+}
+
static int bd71828_probe(struct platform_device *pdev)
{
- int i, j, ret;
+ int i, j, ret, num_regulators;
struct regulator_config config = {
.dev = pdev->dev.parent,
};
+ enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;
+ struct bd71828_regulator_data *rdata;
config.regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!config.regmap)
return -ENODEV;
- for (i = 0; i < ARRAY_SIZE(bd71828_rdata); i++) {
+ switch (chip) {
+ case ROHM_CHIP_TYPE_BD72720:
+ rdata = devm_kmemdup(&pdev->dev, bd72720_rdata,
+ sizeof(bd72720_rdata), GFP_KERNEL);
+ if (!rdata)
+ return -ENOMEM;
+
+ ret = bd72720_dt_parse(&pdev->dev, &rdata[BD72720_BUCK10_DESC_INDEX].desc,
+ config.regmap);
+ if (ret)
+ return ret;
+
+ num_regulators = ARRAY_SIZE(bd72720_rdata);
+ break;
+
+ case ROHM_CHIP_TYPE_BD71828:
+ rdata = devm_kmemdup(&pdev->dev, bd71828_rdata,
+ sizeof(bd71828_rdata), GFP_KERNEL);
+ if (!rdata)
+ return -ENOMEM;
+
+ num_regulators = ARRAY_SIZE(bd71828_rdata);
+
+ break;
+ default:
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "Unsupported device\n");
+ }
+
+ for (i = 0; i < num_regulators; i++) {
struct regulator_dev *rdev;
- const struct bd71828_regulator_data *rd;
+ struct bd71828_regulator_data *rd;
+
+ rd = &rdata[i];
- rd = &bd71828_rdata[i];
+ config.driver_data = rd;
rdev = devm_regulator_register(&pdev->dev,
&rd->desc, &config);
if (IS_ERR(rdev))
@@ -714,12 +1690,20 @@ static int bd71828_probe(struct platform_device *pdev)
return 0;
}
+static const struct platform_device_id bd71828_pmic_id[] = {
+ { "bd71828-pmic", ROHM_CHIP_TYPE_BD71828 },
+ { "bd72720-pmic", ROHM_CHIP_TYPE_BD72720 },
+ { },
+};
+MODULE_DEVICE_TABLE(platform, bd71828_pmic_id);
+
static struct platform_driver bd71828_regulator = {
.driver = {
.name = "bd71828-pmic",
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = bd71828_probe,
+ .id_table = bd71828_pmic_id,
};
module_platform_driver(bd71828_regulator);
@@ -727,4 +1711,3 @@ module_platform_driver(bd71828_regulator);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("BD71828 voltage regulator driver");
MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bd71828-pmic");
--
2.51.1
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^ permalink raw reply related
* [PATCH v5 11/16] gpio: Support ROHM BD72720 gpios
From: Matti Vaittinen @ 2025-11-20 8:23 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1763625920.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 10901 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The ROHM BD72720 has 6 pins which may be configured as GPIOs. The
GPIO1 ... GPIO5 and EPDEN pins. The configuration is done to OTP at the
manufacturing, and it can't be read at runtime. The device-tree is
required to tell the software which of the pins are used as GPIOs.
Keep the pin mapping static regardless the OTP. This way the user-space
can always access the BASE+N for GPIO(N+1) (N = 0 to 4), and BASE + 5
for the EPDEN pin. Do this by setting always the number of GPIOs to 6,
and by using the valid-mask to invalidate the pins which aren't configured
as GPIOs.
First two pins can be set to be either input or output by OTP. Direction
can't be changed by software. Rest of the pins can be set as outputs
only. All of the pins support generating interrupts.
Support the Input/Output state getting/setting and the output mode
configuration (open-drain/push-pull).
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
Revision history:
RFCv1 => :
- No changes
---
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-bd72720.c | 281 ++++++++++++++++++++++++++++++++++++
3 files changed, 291 insertions(+)
create mode 100644 drivers/gpio/gpio-bd72720.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7ee3afbc2b05..0c612c5163c5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1319,6 +1319,15 @@ config GPIO_BD71828
This driver can also be built as a module. If so, the module
will be called gpio-bd71828.
+config GPIO_BD72720
+ tristate "ROHM BD72720 and BD73900 PMIC GPIO support"
+ depends on MFD_ROHM_BD71828
+ help
+ Support for GPIO on ROHM BD72720 and BD73900 PMICs. There are two
+ pins which can be configured to GPI or GPO, and three pins which can
+ be configured to GPO on the ROHM PMIC. The pin configuration is done
+ on OTP at manufacturing.
+
config GPIO_BD9571MWV
tristate "ROHM BD9571 GPIO support"
depends on MFD_BD9571MWV
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ec296fa14bfd..7a5d03db3021 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o
obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o
obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o
+obj-$(CONFIG_GPIO_BD72720) += gpio-bd72720.o
obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o
obj-$(CONFIG_GPIO_BLZP1600) += gpio-blzp1600.o
obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
diff --git a/drivers/gpio/gpio-bd72720.c b/drivers/gpio/gpio-bd72720.c
new file mode 100644
index 000000000000..6549dbf4c7ad
--- /dev/null
+++ b/drivers/gpio/gpio-bd72720.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support to GPIOs on ROHM BD72720 and BD79300
+ * Copyright 2025 ROHM Semiconductors.
+ * Author: Matti Vaittinen <mazziesaccount@gmail.com>
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/rohm-bd72720.h>
+
+#define BD72720_GPIO_OPEN_DRAIN 0
+#define BD72720_GPIO_CMOS BIT(1)
+#define BD72720_INT_GPIO1_IN_SRC 4
+/*
+ * The BD72720 has several "one time programmable" (OTP) configurations which
+ * can be set at manufacturing phase. A set of these options allow using pins
+ * as GPIO. The OTP configuration can't be read at run-time, so drivers rely on
+ * device-tree to advertise the correct options.
+ *
+ * Both DVS[0,1] pins can be configured to be used for:
+ * - OTP0: regulator RUN state control
+ * - OTP1: GPI
+ * - OTP2: GPO
+ * - OTP3: Power sequencer output
+ * Data-sheet also states that these PINs can always be used for IRQ but the
+ * driver limits this by allowing them to be used for IRQs with OTP1 only.
+ *
+ * Pins GPIO_EXTEN0 (GPIO3), GPIO_EXTEN1 (GPIO4), GPIO_FAULT_B (GPIO5) have OTP
+ * options for a specific (non GPIO) purposes, but also an option to configure
+ * them to be used as a GPO.
+ *
+ * OTP settings can be separately configured for each pin.
+ *
+ * DT properties:
+ * "rohm,pin-dvs0" and "rohm,pin-dvs1" can be set to one of the values:
+ * "dvs-input", "gpi", "gpo".
+ *
+ * "rohm,pin-exten0", "rohm,pin-exten1" and "rohm,pin-fault_b" can be set to:
+ * "gpo"
+ */
+
+enum bd72720_gpio_state {
+ BD72720_PIN_UNKNOWN,
+ BD72720_PIN_GPI,
+ BD72720_PIN_GPO,
+};
+
+enum {
+ BD72720_GPIO1,
+ BD72720_GPIO2,
+ BD72720_GPIO3,
+ BD72720_GPIO4,
+ BD72720_GPIO5,
+ BD72720_GPIO_EPDEN,
+ BD72720_NUM_GPIOS
+};
+
+struct bd72720_gpio {
+ /* chip.parent points the MFD which provides DT node and regmap */
+ struct gpio_chip chip;
+ /* dev points to the platform device for devm and prints */
+ struct device *dev;
+ struct regmap *regmap;
+ int gpio_is_input;
+};
+
+static int bd72720gpi_get(struct bd72720_gpio *bdgpio, unsigned int reg_offset)
+{
+ int ret, val, shift;
+
+ ret = regmap_read(bdgpio->regmap, BD72720_REG_INT_ETC1_SRC, &val);
+ if (ret)
+ return ret;
+
+ shift = BD72720_INT_GPIO1_IN_SRC + reg_offset;
+
+ return (val >> shift) & 1;
+}
+
+static int bd72720gpo_get(struct bd72720_gpio *bdgpio,
+ unsigned int offset)
+{
+ const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
+ BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
+ int ret, val;
+
+ ret = regmap_read(bdgpio->regmap, regs[offset], &val);
+ if (ret)
+ return ret;
+
+ return val & BD72720_GPIO_HIGH;
+}
+
+static int bd72720gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+
+ if (BIT(offset) & bdgpio->gpio_is_input)
+ return bd72720gpi_get(bdgpio, offset);
+
+ return bd72720gpo_get(bdgpio, offset);
+}
+
+static int bd72720gpo_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+ const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
+ BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
+
+ if (BIT(offset) & bdgpio->gpio_is_input) {
+ dev_dbg(bdgpio->dev, "pin %d not output.\n", offset);
+ return -EINVAL;
+ }
+
+ if (value)
+ return regmap_set_bits(bdgpio->regmap, regs[offset],
+ BD72720_GPIO_HIGH);
+
+ return regmap_clear_bits(bdgpio->regmap, regs[offset],
+ BD72720_GPIO_HIGH);
+}
+
+static int bd72720_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+ const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
+ BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
+
+ /*
+ * We can only set the output mode, which makes sense only when output
+ * OTP configuration is used.
+ */
+ if (BIT(offset) & bdgpio->gpio_is_input)
+ return -ENOTSUPP;
+
+ switch (pinconf_to_config_param(config)) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ return regmap_update_bits(bdgpio->regmap,
+ regs[offset],
+ BD72720_GPIO_DRIVE_MASK,
+ BD72720_GPIO_OPEN_DRAIN);
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ return regmap_update_bits(bdgpio->regmap,
+ regs[offset],
+ BD72720_GPIO_DRIVE_MASK,
+ BD72720_GPIO_CMOS);
+ default:
+ break;
+ }
+
+ return -ENOTSUPP;
+}
+
+static int bd72720gpo_direction_get(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+
+ if (BIT(offset) & bdgpio->gpio_is_input)
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int bd72720_valid_mask(struct gpio_chip *gc,
+ unsigned long *valid_mask,
+ unsigned int ngpios)
+{
+ static const char * const properties[] = {
+ "rohm,pin-dvs0", "rohm,pin-dvs1", "rohm,pin-exten0",
+ "rohm,pin-exten1", "rohm,pin-fault_b"
+ };
+ struct bd72720_gpio *g = gpiochip_get_data(gc);
+ const char *val;
+ int i, ret;
+
+ *valid_mask = BIT(BD72720_GPIO_EPDEN);
+
+ if (!gc->parent)
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ ret = fwnode_property_read_string(dev_fwnode(gc->parent),
+ properties[i], &val);
+
+ if (ret) {
+ if (ret == -EINVAL)
+ continue;
+
+ dev_err(g->dev, "pin %d (%s), bad configuration\n", i,
+ properties[i]);
+
+ return ret;
+ }
+
+ if (strcmp(val, "gpi") == 0) {
+ if (i != BD72720_GPIO1 && i != BD72720_GPIO2) {
+ dev_warn(g->dev,
+ "pin %d (%s) does not support INPUT mode",
+ i, properties[i]);
+ continue;
+ }
+
+ *valid_mask |= BIT(i);
+ g->gpio_is_input |= BIT(i);
+ } else if (strcmp(val, "gpo") == 0) {
+ *valid_mask |= BIT(i);
+ }
+ }
+
+ return 0;
+}
+
+/* Template for GPIO chip */
+static const struct gpio_chip bd72720gpo_chip = {
+ .label = "bd72720",
+ .owner = THIS_MODULE,
+ .get = bd72720gpio_get,
+ .get_direction = bd72720gpo_direction_get,
+ .set = bd72720gpo_set,
+ .set_config = bd72720_gpio_set_config,
+ .init_valid_mask = bd72720_valid_mask,
+ .can_sleep = true,
+ .ngpio = BD72720_NUM_GPIOS,
+ .base = -1,
+};
+
+static int gpo_bd72720_probe(struct platform_device *pdev)
+{
+ struct bd72720_gpio *g;
+ struct device *parent, *dev;
+
+ /*
+ * Bind devm lifetime to this platform device => use dev for devm.
+ * also the prints should originate from this device.
+ */
+ dev = &pdev->dev;
+ /* The device-tree and regmap come from MFD => use parent for that */
+ parent = dev->parent;
+
+ g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+ if (!g)
+ return -ENOMEM;
+
+ g->chip = bd72720gpo_chip;
+ g->dev = dev;
+ g->chip.parent = parent;
+ g->regmap = dev_get_regmap(parent, NULL);
+
+ return devm_gpiochip_add_data(dev, &g->chip, g);
+}
+
+static const struct platform_device_id bd72720_gpio_id[] = {
+ { "bd72720-gpio" },
+ { },
+};
+MODULE_DEVICE_TABLE(platform, bd72720_gpio_id);
+
+static struct platform_driver gpo_bd72720_driver = {
+ .driver = {
+ .name = "bd72720-gpio",
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = gpo_bd72720_probe,
+ .id_table = bd72720_gpio_id,
+};
+module_platform_driver(gpo_bd72720_driver);
+
+MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
+MODULE_DESCRIPTION("GPIO interface for BD72720 and BD73900");
+MODULE_LICENSE("GPL");
--
2.51.1
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
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