* 歌・ダンス等のスクール事業 FC説明会
From: 株式会社 K Village @ 2025-12-04 2:38 UTC (permalink / raw)
To: linux-rtc
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^ permalink raw reply
* rtc-max31335.c: use of IS_REACHABLE()
From: Randy Dunlap @ 2025-12-04 1:38 UTC (permalink / raw)
To: Alexandre Belloni, linux-rtc, Antoniu Miclaus
Hi,
Just checking: should these be IS_REACHABLE(CONFIG_HWMON) ?
If not, what "HWMON" is being referenced here?
596:#if IS_REACHABLE(HWMON)
677:#if IS_REACHABLE(HWMON)
732:#if IS_REACHABLE(HWMON)
thanks.
--
~Randy
^ permalink raw reply
* Re: [PATCH] MAINTAINERS: drop unneeded file entry in NVIDIA VRS RTC DRIVER
From: Thierry Reding @ 2025-12-01 14:11 UTC (permalink / raw)
To: Lukas Bulwahn
Cc: Shubhi Garg, Alexandre Belloni, linux-tegra, linux-rtc,
Jon Hunter, kernel-janitors, linux-kernel, Lukas Bulwahn
In-Reply-To: <20251110073544.443816-1-lukas.bulwahn@redhat.com>
[-- Attachment #1: Type: text/plain, Size: 872 bytes --]
On Mon, Nov 10, 2025 at 08:35:44AM +0100, Lukas Bulwahn wrote:
> From: Lukas Bulwahn <lukas.bulwahn@redhat.com>
>
> Commit 9d6d6b06933c ("rtc: nvvrs: add NVIDIA VRS RTC device driver") adds
> the section NVIDIA VRS RTC DRIVER in MAINTAINERS, which refers to the
> non-existing file include/linux/rtc/rtc-nvidia-vrs10.h
>
> Note, with the changes of v6 to v7 of the patch series adding the driver,
> the content of this include file was moved into the driver file, and the
> include file was dropped from that patch. It was simply missed to adjust
> the section in MAINTAINERS that was newly added with that patch.
>
> Drop the file entry to this non-existing file accordingly now.
>
> Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com>
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v6 04/17] dt-bindings: battery: Voltage drop properties
From: Linus Walleij @ 2025-12-01 13:21 UTC (permalink / raw)
To: Matti Vaittinen
Cc: Matti Vaittinen, Lee Jones, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sebastian Reichel,
Liam Girdwood, Mark Brown, Michael Turquette, Stephen Boyd,
Linus Walleij, Bartosz Golaszewski, Alexandre Belloni, linux-leds,
devicetree, linux-kernel, linux-pm, linux-clk, linux-gpio,
linux-rtc, Andreas Kemnade
In-Reply-To: <3f1e43285f58630eb0164857533ccfea9ea628ab.1764241265.git.mazziesaccount@gmail.com>
On Thu, Nov 27, 2025 at 12:18 PM Matti Vaittinen
<matti.vaittinen@linux.dev> wrote:
> From: Matti Vaittinen <mazziesaccount@gmail.com>
>
> ROHM has developed a so called "zero-correction" -algorithm to improve
> the fuel-gauging accuracy close to the point where battery is depleted.
> This relies on battery specific "VDR" (voltage drop rate) tables, which
> are measured from the battery, and which describe the voltage drop rate.
> More thorough explanation about the "zero correction" and "VDR"
> parameters is here:
> https://lore.kernel.org/all/676253b9-ff69-7891-1f26-a8b5bb5a421b@fi.rohmeurope.com/
>
> Document the VDR zero-correction specific battery properties used by the
> BD71815, BD71828, BD72720 and some other ROHM chargers. (Note, charger
> drivers aren't upstream yet).
>
> Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
I like this even more!
Reviewed-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 4/4] rtc: zynqmp: use dynamic max and min offset ranges
From: Tomas Melin @ 2025-12-01 12:50 UTC (permalink / raw)
To: Alexandre Belloni, Michal Simek
Cc: linux-rtc, linux-arm-kernel, linux-kernel, Tomas Melin
In-Reply-To: <20251201-zynqmp-rtc-updates-v1-0-33875c1e385b@vaisala.com>
Maximum and minimum offsets in ppb that can be handled are dependent on
the rtc clock frequency and what can fit in the 16-bit register field.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
drivers/rtc/rtc-zynqmp.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
index 3bc8831ba2c4c4c701a49506b67ae6174f3ade3d..0cebc99b15a6de2440a60afc2bd1769eccfa84b3 100644
--- a/drivers/rtc/rtc-zynqmp.c
+++ b/drivers/rtc/rtc-zynqmp.c
@@ -44,8 +44,6 @@
#define RTC_FR_MASK 0xF0000
#define RTC_FR_MAX_TICKS 16
#define RTC_PPB 1000000000LL
-#define RTC_MIN_OFFSET -32768000
-#define RTC_MAX_OFFSET 32767000
struct xlnx_rtc_dev {
struct rtc_device *rtc;
@@ -215,12 +213,12 @@ static int xlnx_rtc_set_offset(struct device *dev, long offset)
/* ticks to reach RTC_PPB */
tick_mult = DIV_ROUND_CLOSEST(RTC_PPB, xrtcdev->freq);
- if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET)
- return -ERANGE;
-
/* Number ticks for given offset */
max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
+ if (freq + max_tick > RTC_TICK_MASK || (freq + max_tick < 1))
+ return -ERANGE;
+
/* Number fractional ticks for given offset */
if (fract_offset) {
/* round up here so we stay below a full tick */
--
2.47.3
^ permalink raw reply related
* [PATCH 3/4] rtc: zynqmp: rework set_offset
From: Tomas Melin @ 2025-12-01 12:50 UTC (permalink / raw)
To: Alexandre Belloni, Michal Simek
Cc: linux-rtc, linux-arm-kernel, linux-kernel, Tomas Melin
In-Reply-To: <20251201-zynqmp-rtc-updates-v1-0-33875c1e385b@vaisala.com>
set_offset was using remainder of do_div as tick_mult which resulted in
wrong offset. Calibration value also assumed builtin calibration default.
Update fract_offset to correctly calculate the value for
negative offset and replace the for loop with division.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
drivers/rtc/rtc-zynqmp.c | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
index 7af5f6f99538f961a53ff56bfc656c907611b900..3bc8831ba2c4c4c701a49506b67ae6174f3ade3d 100644
--- a/drivers/rtc/rtc-zynqmp.c
+++ b/drivers/rtc/rtc-zynqmp.c
@@ -208,13 +208,13 @@ static int xlnx_rtc_read_offset(struct device *dev, long *offset)
static int xlnx_rtc_set_offset(struct device *dev, long offset)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
- unsigned long long rtc_ppb = RTC_PPB;
- unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
+ unsigned int calibval, tick_mult, fract_part;
unsigned char fract_tick = 0;
- unsigned int calibval;
- short int max_tick;
- int fract_offset;
+ int freq = xrtcdev->freq;
+ int max_tick, fract_offset;
+ /* ticks to reach RTC_PPB */
+ tick_mult = DIV_ROUND_CLOSEST(RTC_PPB, xrtcdev->freq);
if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET)
return -ERANGE;
@@ -223,29 +223,22 @@ static int xlnx_rtc_set_offset(struct device *dev, long offset)
/* Number fractional ticks for given offset */
if (fract_offset) {
+ /* round up here so we stay below a full tick */
+ fract_part = DIV_ROUND_UP(tick_mult, RTC_FR_MAX_TICKS);
if (fract_offset < 0) {
- fract_offset = fract_offset + tick_mult;
+ fract_offset += (fract_part * RTC_FR_MAX_TICKS);
max_tick--;
}
- if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
- for (fract_tick = 1; fract_tick < 16; fract_tick++) {
- if (fract_offset <=
- (fract_tick *
- (tick_mult / RTC_FR_MAX_TICKS)))
- break;
- }
- }
+ fract_tick = fract_offset / fract_part;
}
/* Zynqmp RTC uses second and fractional tick
* counters for compensation
*/
- calibval = max_tick + RTC_CALIB_DEF;
+ calibval = max_tick + freq;
if (fract_tick)
- calibval |= RTC_FR_EN;
-
- calibval |= (fract_tick << RTC_FR_DATSHIFT);
+ calibval |= (RTC_FR_EN | (fract_tick << RTC_FR_DATSHIFT));
writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
--
2.47.3
^ permalink raw reply related
* [PATCH 2/4] rtc: zynqmp: rework read_offset
From: Tomas Melin @ 2025-12-01 12:50 UTC (permalink / raw)
To: Alexandre Belloni, Michal Simek
Cc: linux-rtc, linux-arm-kernel, linux-kernel, Tomas Melin
In-Reply-To: <20251201-zynqmp-rtc-updates-v1-0-33875c1e385b@vaisala.com>
read_offset() was using static frequency for determining
the tick offset. It was also using remainder from do_div()
operation as tick_mult value which caused the offset to be
incorrect.
At the same time, rework function to improve readability.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
drivers/rtc/rtc-zynqmp.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
index 856bc1678e7d31144f320ae9f75fc58c742a2a64..7af5f6f99538f961a53ff56bfc656c907611b900 100644
--- a/drivers/rtc/rtc-zynqmp.c
+++ b/drivers/rtc/rtc-zynqmp.c
@@ -178,21 +178,28 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
static int xlnx_rtc_read_offset(struct device *dev, long *offset)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
- unsigned long long rtc_ppb = RTC_PPB;
- unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
- unsigned int calibval;
+ unsigned int calibval, fract_data, fract_part;
+ int max_tick, tick_mult;
+ int freq = xrtcdev->freq;
long offset_val;
+ /* ticks to reach RTC_PPB */
+ tick_mult = DIV_ROUND_CLOSEST(RTC_PPB, freq);
+
calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
/* Offset with seconds ticks */
- offset_val = calibval & RTC_TICK_MASK;
- offset_val = offset_val - RTC_CALIB_DEF;
- offset_val = offset_val * tick_mult;
+ max_tick = calibval & RTC_TICK_MASK;
+ offset_val = max_tick - freq;
+ /* Convert to ppb */
+ offset_val *= tick_mult;
/* Offset with fractional ticks */
- if (calibval & RTC_FR_EN)
- offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
- * (tick_mult / RTC_FR_MAX_TICKS);
+ if (calibval & RTC_FR_EN) {
+ fract_data = (calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT;
+ fract_part = DIV_ROUND_UP(tick_mult, RTC_FR_MAX_TICKS);
+ offset_val += (fract_part * fract_data);
+ }
+
*offset = offset_val;
return 0;
--
2.47.3
^ permalink raw reply related
* [PATCH 1/4] rtc: zynqmp: correct frequency value
From: Tomas Melin @ 2025-12-01 12:50 UTC (permalink / raw)
To: Alexandre Belloni, Michal Simek
Cc: linux-rtc, linux-arm-kernel, linux-kernel, Tomas Melin
In-Reply-To: <20251201-zynqmp-rtc-updates-v1-0-33875c1e385b@vaisala.com>
Fix calibration value in case a clock reference is provided.
The actual calibration value written into register is
frequency - 1.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
drivers/rtc/rtc-zynqmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
index 3baa2b481d9f2008750046005283b98a0d546c5c..856bc1678e7d31144f320ae9f75fc58c742a2a64 100644
--- a/drivers/rtc/rtc-zynqmp.c
+++ b/drivers/rtc/rtc-zynqmp.c
@@ -345,7 +345,10 @@ static int xlnx_rtc_probe(struct platform_device *pdev)
&xrtcdev->freq);
if (ret)
xrtcdev->freq = RTC_CALIB_DEF;
+ } else {
+ xrtcdev->freq--;
}
+
ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
if (!ret)
writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
--
2.47.3
^ permalink raw reply related
* [PATCH 0/4] rtc: zynqmp: fixes for read and set offset
From: Tomas Melin @ 2025-12-01 12:50 UTC (permalink / raw)
To: Alexandre Belloni, Michal Simek
Cc: linux-rtc, linux-arm-kernel, linux-kernel, Tomas Melin
Add improvements for read and set offset functions.
The basic functionality is still the same, but offset correction values
are now updated to match with expected.
The RTC calibration value operates with full ticks,
and fractional ticks which are a 1/16 of a full tick.
The 16 lowest bits in the calibration registers are for the full ticks
and value matches the external oscillator in Hz. Through that,
the maximum and minimum offset values can be calculated dynamically,
as they depend on the input frequency used.
For docs on the calibration register, see
https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/CALIB_READ-RTC-Register
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
Tomas Melin (4):
rtc: zynqmp: correct frequency value
rtc: zynqmp: rework read_offset
rtc: zynqmp: rework set_offset
rtc: zynqmp: use dynamic max and min offset ranges
drivers/rtc/rtc-zynqmp.c | 65 ++++++++++++++++++++++++------------------------
1 file changed, 33 insertions(+), 32 deletions(-)
---
base-commit: cd635e33b0113287c94021be53d2a7c61a1614e9
change-id: 20251201-zynqmp-rtc-updates-d260364cc01b
Best regards,
--
Tomas Melin <tomas.melin@vaisala.com>
^ permalink raw reply
* Re: [PATCH] MAINTAINERS: drop unneeded file entry in NVIDIA VRS RTC DRIVER
From: Shubhi Garg @ 2025-12-01 9:00 UTC (permalink / raw)
To: Jon Hunter, Lukas Bulwahn, Alexandre Belloni, linux-tegra,
linux-rtc
Cc: kernel-janitors, linux-kernel, Lukas Bulwahn
In-Reply-To: <42ce1ab1-8334-4dd4-8301-1ae84a7786b6@nvidia.com>
On 10/11/25 5:17 pm, Jon Hunter wrote:
>
> On 10/11/2025 07:35, Lukas Bulwahn wrote:
>> From: Lukas Bulwahn <lukas.bulwahn@redhat.com>
>>
>> Commit 9d6d6b06933c ("rtc: nvvrs: add NVIDIA VRS RTC device driver") adds
>> the section NVIDIA VRS RTC DRIVER in MAINTAINERS, which refers to the
>> non-existing file include/linux/rtc/rtc-nvidia-vrs10.h
>>
>> Note, with the changes of v6 to v7 of the patch series adding the driver,
>> the content of this include file was moved into the driver file, and the
>> include file was dropped from that patch. It was simply missed to adjust
>> the section in MAINTAINERS that was newly added with that patch.
>>
>> Drop the file entry to this non-existing file accordingly now.
>>
>> Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com>
>> ---
>> MAINTAINERS | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 2a881629003c..b2b55947efef 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -18586,7 +18586,6 @@ L: linux-tegra@vger.kernel.org
>> S: Maintained
>> F: Documentation/devicetree/bindings/rtc/nvidia,vrs-10.yaml
>> F: drivers/rtc/rtc-nvidia-vrs10.c
>> -F: include/linux/rtc/rtc-nvidia-vrs10.h
>> NVIDIA WMI EC BACKLIGHT DRIVER
>> M: Daniel Dadap <ddadap@nvidia.com>
>
>
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>
> Thanks!
> Jon
>
Reviewed-by: Shubhi Garg <shgarg@nvidia.com>
--
Regards,
Shubhi
^ permalink raw reply
* [PATCH RESEND] rtc: max31335: Fix ignored return value in set_alarm
From: Nuno Sá via B4 Relay @ 2025-11-28 16:36 UTC (permalink / raw)
To: linux-rtc; +Cc: Alexandre Belloni, Guenter Roeck, Antoniu Miclaus
From: Nuno Sá <nuno.sa@analog.com>
Return the result from regmap_update_bits() instead of ignoring it
and always returning 0.
Fixes: dedaf03b99d6 ("rtc: max31335: add driver support")
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
drivers/rtc/rtc-max31335.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/rtc/rtc-max31335.c b/drivers/rtc/rtc-max31335.c
index dfb5bad3a369..23b7bf16b4cd 100644
--- a/drivers/rtc/rtc-max31335.c
+++ b/drivers/rtc/rtc-max31335.c
@@ -391,10 +391,8 @@ static int max31335_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
if (ret)
return ret;
- ret = regmap_update_bits(max31335->regmap, max31335->chip->int_status_reg,
- MAX31335_STATUS1_A1F, 0);
-
- return 0;
+ return regmap_update_bits(max31335->regmap, max31335->chip->int_status_reg,
+ MAX31335_STATUS1_A1F, 0);
}
static int max31335_alarm_irq_enable(struct device *dev, unsigned int enabled)
---
base-commit: 9db26d5855d0374d4652487bfb5aacf40821c469
change-id: 20251029-max31335-handler-error-65a286c74289
--
Thanks!
- Nuno Sá
--
Nuno Sá <nuno.sa@analog.com>
^ permalink raw reply related
* Re: [PATCH v5 05/11] mfd: macsmc: Add new __SMC_KEY macro
From: James Calligeros @ 2025-11-28 10:36 UTC (permalink / raw)
To: Lee Jones
Cc: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Neal Gompa,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Belloni,
Jean Delvare, Guenter Roeck, Dmitry Torokhov, Jonathan Corbet,
asahi, linux-arm-kernel, devicetree, linux-kernel, linux-rtc,
linux-hwmon, linux-input, linux-doc
In-Reply-To: <20251120134445.GC661940@google.com>
On Thursday, 20 November 2025 11:44:45 pm Australian Eastern Standard Time Lee
Jones wrote:
> On Wed, 12 Nov 2025, James Calligeros wrote:
> > When using the _SMC_KEY macro in switch/case statements, GCC 15.2.1 errors
> > out with 'case label does not reduce to an integer constant'. Introduce
> > a new __SMC_KEY macro that can be used instead.
> >
> > Signed-off-by: James Calligeros <jcalligeros99@gmail.com>
> > ---
> >
> > include/linux/mfd/macsmc.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/include/linux/mfd/macsmc.h b/include/linux/mfd/macsmc.h
> > index 6b13f01a8592..f6f80c33b5cf 100644
> > --- a/include/linux/mfd/macsmc.h
> > +++ b/include/linux/mfd/macsmc.h
> > @@ -41,6 +41,7 @@ typedef u32 smc_key;
> >
> > */
> >
> > #define SMC_KEY(s) (smc_key)(_SMC_KEY(#s))
> > #define _SMC_KEY(s) (((s)[0] << 24) | ((s)[1] << 16) | ((s)[2] << 8) |
> > (s)[3])>
> > +#define __SMC_KEY(a, b, c, d) (((u32)(a) << 24) | ((u32)(b) << 16) |
> > ((u32)(c) << 8) | ((u32)(d)))
> Are we expecting users/consumers to be able to tell the difference
> between SMC_KEY and __SMC_KEY (assuming that _SMC_KEY is just an
> internal)?
_SMC_KEY is used in the gpio driver, and I would have used it here too if not
for GCC complaining about it. I wouldn't expect anyone to want to use
__SMC_KEY outside of the specific use case this commit addresses given the
suboptimal ergonomics.
> I have not tested this and it is just off the top of my head, but does
> this work:
>
> #define _SMC_KEY(s) __SMC_KEY((s)[0], (s)[1], (s)[2], (s)[3])
This works fine on a smattering of M1 and M2 series machines. I can submit a
v6 with this and the hwmon driver dropped if need be.
Regards,
James
^ permalink raw reply
* Re: [PATCH v5 06/11] hwmon: Add Apple Silicon SMC hwmon driver
From: Dan Carpenter @ 2025-11-28 8:10 UTC (permalink / raw)
To: James Calligeros
Cc: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Neal Gompa,
Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Alexandre Belloni, Jean Delvare, Guenter Roeck, Dmitry Torokhov,
Jonathan Corbet, asahi, linux-arm-kernel, devicetree,
linux-kernel, linux-rtc, linux-hwmon, linux-input, linux-doc
In-Reply-To: <20251112-macsmc-subdevs-v5-6-728e4b91fe81@gmail.com>
On Wed, Nov 12, 2025 at 09:16:52PM +1000, James Calligeros wrote:
> +static int macsmc_hwmon_populate_sensors(struct macsmc_hwmon *hwmon,
> + struct device_node *hwmon_node)
> +{
> + struct device_node *key_node __maybe_unused;
The for_each_child_of_node_with_prefix() macros declare key_node so this
declaration is never used so far as I can see. I thought Sparse had a
warning where we declared shadow variables where two variables have the
same name but it doesn't complain here. #strange
> + struct macsmc_hwmon_sensor *sensor;
> + u32 n_current = 0, n_fan = 0, n_power = 0, n_temperature = 0, n_voltage = 0;
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "current-") {
^^^^^^^^
regards,
dan carpenter
> + n_current++;
> + }
> +
> + if (n_current) {
> + hwmon->curr.sensors = devm_kcalloc(hwmon->dev, n_current,
> + sizeof(struct macsmc_hwmon_sensor), GFP_KERNEL);
> + if (!hwmon->curr.sensors)
> + return -ENOMEM;
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "current-") {
> + sensor = &hwmon->curr.sensors[hwmon->curr.count];
> + if (!macsmc_hwmon_create_sensor(hwmon->dev, hwmon->smc, key_node, sensor)) {
> + sensor->attrs = HWMON_C_INPUT;
> +
> + if (*sensor->label)
> + sensor->attrs |= HWMON_C_LABEL;
> +
> + hwmon->curr.count++;
> + }
> + }
> + }
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "fan-") {
> + n_fan++;
> + }
> +
> + if (n_fan) {
> + hwmon->fan.fans = devm_kcalloc(hwmon->dev, n_fan,
> + sizeof(struct macsmc_hwmon_fan), GFP_KERNEL);
> + if (!hwmon->fan.fans)
> + return -ENOMEM;
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "fan-") {
> + if (!macsmc_hwmon_create_fan(hwmon->dev, hwmon->smc, key_node,
> + &hwmon->fan.fans[hwmon->fan.count]))
> + hwmon->fan.count++;
> + }
> + }
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "power-") {
> + n_power++;
> + }
> +
> + if (n_power) {
> + hwmon->power.sensors = devm_kcalloc(hwmon->dev, n_power,
> + sizeof(struct macsmc_hwmon_sensor), GFP_KERNEL);
> + if (!hwmon->power.sensors)
> + return -ENOMEM;
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "power-") {
> + sensor = &hwmon->power.sensors[hwmon->power.count];
> + if (!macsmc_hwmon_create_sensor(hwmon->dev, hwmon->smc, key_node, sensor)) {
> + sensor->attrs = HWMON_P_INPUT;
> +
> + if (*sensor->label)
> + sensor->attrs |= HWMON_P_LABEL;
> +
> + hwmon->power.count++;
> + }
> + }
> + }
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "temperature-") {
> + n_temperature++;
> + }
> +
> + if (n_temperature) {
> + hwmon->temp.sensors = devm_kcalloc(hwmon->dev, n_temperature,
> + sizeof(struct macsmc_hwmon_sensor), GFP_KERNEL);
> + if (!hwmon->temp.sensors)
> + return -ENOMEM;
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "temperature-") {
> + sensor = &hwmon->temp.sensors[hwmon->temp.count];
> + if (!macsmc_hwmon_create_sensor(hwmon->dev, hwmon->smc, key_node, sensor)) {
> + sensor->attrs = HWMON_T_INPUT;
> +
> + if (*sensor->label)
> + sensor->attrs |= HWMON_T_LABEL;
> +
> + hwmon->temp.count++;
> + }
> + }
> + }
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "voltage-") {
> + n_voltage++;
> + }
> +
> + if (n_voltage) {
> + hwmon->volt.sensors = devm_kcalloc(hwmon->dev, n_voltage,
> + sizeof(struct macsmc_hwmon_sensor), GFP_KERNEL);
> + if (!hwmon->volt.sensors)
> + return -ENOMEM;
> +
> + for_each_child_of_node_with_prefix(hwmon_node, key_node, "volt-") {
> + sensor = &hwmon->temp.sensors[hwmon->temp.count];
> + if (!macsmc_hwmon_create_sensor(hwmon->dev, hwmon->smc, key_node, sensor)) {
> + sensor->attrs = HWMON_I_INPUT;
> +
> + if (*sensor->label)
> + sensor->attrs |= HWMON_I_LABEL;
> +
> + hwmon->volt.count++;
> + }
> + }
> + }
> +
> + return 0;
> +}
^ permalink raw reply
* RE: [EXT] Re: [PATCH v7 1/2] dt-bindings: rtc: Add pcf85053 support
From: Lakshay Piplani @ 2025-11-27 17:15 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: linux-rtc@vger.kernel.org, Priyanka Jain, Conor Dooley,
Vikash Bansal, krzk+dt@kernel.org, Shashank Rebbapragada,
Pankit Garg, linux-kernel@vger.kernel.org, conor+dt@kernel.org,
alexandre.belloni@bootlin.com, devicetree@vger.kernel.org
In-Reply-To: <176424931148.3999997.8332932232270023828.robh@kernel.org>
> -----Original Message-----
> From: Rob Herring (Arm) <robh@kernel.org>
> Sent: Thursday, November 27, 2025 6:45 PM
> To: Lakshay Piplani <lakshay.piplani@nxp.com>
> Cc: linux-rtc@vger.kernel.org; Priyanka Jain <priyanka.jain@nxp.com>; Conor
> Dooley <conor.dooley@microchip.com>; Vikash Bansal
> <vikash.bansal@nxp.com>; krzk+dt@kernel.org; Shashank Rebbapragada
> <shashank.rebbapragada@nxp.com>; Pankit Garg <pankit.garg@nxp.com>;
> linux-kernel@vger.kernel.org; conor+dt@kernel.org;
> alexandre.belloni@bootlin.com; devicetree@vger.kernel.org
> Subject: [EXT] Re: [PATCH v7 1/2] dt-bindings: rtc: Add pcf85053 support
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> On Thu, 27 Nov 2025 17:34:55 +0530, Lakshay Piplani wrote:
> > Add device tree bindings for NXP PCF85053 RTC chip.
> >
> > Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
> > Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > V6 -> V7: - no changes
> > - Added Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > V5 -> V6: - Dropped driver-specific commentary from property descriptions.
> > - Simplified and clarified descriptions for better readability.
> > V4 -> V5: - Updated schema validation logic to enforce correct combinations
> of
> > 'nxp,interface' and 'nxp,write-access' using oneOf clauses.
> > - Refined property descriptions for clarity and hardware alignment.
> > V3 -> V4: Add dedicated nxp,pcf85053.yaml.
> > Remove entry from trivial-rtc.yaml.
> > V2 -> V3: Moved MAINTAINERS file changes to the driver patch
> > V1 -> V2: Handled dt-bindings by trivial-rtc.yaml
> >
> > .../devicetree/bindings/rtc/nxp,pcf85053.yaml | 114
> > ++++++++++++++++++
> > 1 file changed, 114 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/rtc/nxp,pcf85053.yaml
> >
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb:
> /example-0/soc/thermal-sensor@c263000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb:
> /example-0/soc/thermal-sensor@c263000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb:
> /example-0/soc/thermal-sensor@c265000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb:
> /example-0/soc/thermal-sensor@c265000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb:
> /example-0/soc/thermal-sensor@c263000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb:
> /example-0/soc/thermal-sensor@c263000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb:
> /example-0/soc/thermal-sensor@c265000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
> Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb:
> /example-0/soc/thermal-sensor@c265000: failed to match any schema with
> compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
>
> doc reference errors (make refcheckdocs):
>
> See
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw
> ork.ozlabs.org%2Fproject%2Fdevicetree-
> bindings%2Fpatch%2F20251127120456.1849177-1-
> lakshay.piplani%40nxp.com&data=05%7C02%7Clakshay.piplani%40nxp.com%
> 7C6d7bbae4a787415e631708de2db700c9%7C686ea1d3bc2b4c6fa92cd99c5c3
> 01635%7C0%7C0%7C638998461167266618%7CUnknown%7CTWFpbGZsb3d8
> eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIj
> oiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=Pps7Ic5ozHTrXGDeb
> lYEOBSy9MKZo6iJi5zhHjGB94k%3D&reserved=0
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your
> schema.
Hi Rob,
Thanks for the review.
I have updated dtschema to the latest version and checked the binding.
The reported errors are not related to the patch I submitted.
Additionally, this patch has been tested on the latest mainline kernel.
Thanks,
Lakshay
^ permalink raw reply
* Re: [PATCH v7 1/2] dt-bindings: rtc: Add pcf85053 support
From: Rob Herring (Arm) @ 2025-11-27 13:15 UTC (permalink / raw)
To: Lakshay Piplani
Cc: linux-rtc, priyanka.jain, Conor Dooley, vikash.bansal, krzk+dt,
shashank.rebbapragada, Pankit Garg, linux-kernel, conor+dt,
alexandre.belloni, devicetree
In-Reply-To: <20251127120456.1849177-1-lakshay.piplani@nxp.com>
On Thu, 27 Nov 2025 17:34:55 +0530, Lakshay Piplani wrote:
> Add device tree bindings for NXP PCF85053 RTC chip.
>
> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
> Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> V6 -> V7: - no changes
> - Added Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> V5 -> V6: - Dropped driver-specific commentary from property descriptions.
> - Simplified and clarified descriptions for better readability.
> V4 -> V5: - Updated schema validation logic to enforce correct combinations of
> 'nxp,interface' and 'nxp,write-access' using oneOf clauses.
> - Refined property descriptions for clarity and hardware alignment.
> V3 -> V4: Add dedicated nxp,pcf85053.yaml.
> Remove entry from trivial-rtc.yaml.
> V2 -> V3: Moved MAINTAINERS file changes to the driver patch
> V1 -> V2: Handled dt-bindings by trivial-rtc.yaml
>
> .../devicetree/bindings/rtc/nxp,pcf85053.yaml | 114 ++++++++++++++++++
> 1 file changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85053.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20251127120456.1849177-1-lakshay.piplani@nxp.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH v6 01/17] dt-bindings: regulator: ROHM BD72720
From: Rob Herring (Arm) @ 2025-11-27 13:00 UTC (permalink / raw)
To: Matti Vaittinen
Cc: Matti Vaittinen, Mark Brown, linux-leds, linux-gpio,
Linus Walleij, Alexandre Belloni, linux-pm, linux-rtc, linux-clk,
Krzysztof Kozlowski, Liam Girdwood, devicetree, Lee Jones,
Stephen Boyd, Pavel Machek, Bartosz Golaszewski,
Sebastian Reichel, Michael Turquette, linux-kernel, Conor Dooley,
Andreas Kemnade, Matti Vaittinen
In-Reply-To: <28726d1e0573a6efb6e70716a23ba27c4fc93c6d.1764241265.git.mazziesaccount@gmail.com>
On Thu, 27 Nov 2025 13:16:59 +0200, Matti Vaittinen wrote:
> From: Matti Vaittinen <mazziesaccount@gmail.com>
>
> The ROHM BD72720 is a new PMIC with 10 BUCk and 11 LDO regulators.
>
> The BD72720 is designed to support using the BUCK10 as a supply for
> the LDOs 1 to 4. When the BUCK10 is used for this, it can be set to a
> LDON_HEAD mode. In this mode, the BUCK10 voltage can't be controlled by
> software, but the voltage is adjusted by PMIC to match the LDO1 .. LDO4
> voltages with a given offset. Offset can be 50mV .. 300mV and is
> changeable at 50mV steps.
>
> Add 'ldon-head-microvolt' property to denote a board which is designed
> to utilize the LDON_HEAD mode.
>
> All other properties are already existing.
>
> Add dt-binding doc for ROHM BD72720 regulators to make it usable.
>
> Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
>
> ---
> Revision history:
> v4 =>
> - No changes
>
> v3 => v4:
> - Drop type from ldon-head
> - Fix the name patterns for regulator nodes and names
>
> v2 => v3:
> - drop unnecessary descriptions
> - use microvolts for the 'ldon-head' dt-property
>
> RFCv1 => v2:
> - No changes
> ---
> .../regulator/rohm,bd72720-regulator.yaml | 148 ++++++++++++++++++
> 1 file changed, 148 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
Warning: Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml references a file that doesn't exist: Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml: Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/28726d1e0573a6efb6e70716a23ba27c4fc93c6d.1764241265.git.mazziesaccount@gmail.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* [PATCH v7 2/2] rtc: Add NXP PCF85053 driver support
From: Lakshay Piplani @ 2025-11-27 12:04 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani, Daniel Aguirre, Pankit Garg
In-Reply-To: <20251127120456.1849177-1-lakshay.piplani@nxp.com>
PCF85053 is i2c based RTC which supports timer and calendar
functionality.
Features supported:
1. Read/Write time
2. Get/Set Alarm
3. Wakeup Source
4. Generate up to 32768Hz clock output
5. Primary/Secondary i2c bus
Signed-off-by: Daniel Aguirre <daniel.aguirre@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
---
V6 -> V7: - Addressed minor cleanups from review: use dev_get_drvdata()/dev_set_drvdata()
consistently, fix alarm IRQ dev_id handling, and switch to devm_device_init_wakeup().
- Simplified time/alarm programming by forcing 24h + binary mode in hardware,
dropping complex 12h/BCD handling in setters.
- Documented the 2000–2099 supported year range, explaining how the 00–99 year
register maps to leap-year behavior in the device.
V5 -> V6: no changes
V4 -> V5: no changes
V3 -> V4: - Handle multi-host ownership explicitly using primary/secondary bus hadling.
- Probe no longer changes any CTRL bits unconditionally and do not clear ST/AF/OF
avoiding lost interrupts or silent mode changes.
- Read/Set time & alarm now respect HF(12/24h) and DM(BCD/BIN) converting
hour fields correctly for all combinations.
- Minor changes: drop noisy warnings, tidy error paths/comments.
V2 -> V3: Add MAINTAINERS file changes to this patch
V1 -> V2: no changes
MAINTAINERS | 7 +
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-pcf85053.c | 717 +++++++++++++++++++++++++++++++++++++
4 files changed, 735 insertions(+)
create mode 100644 drivers/rtc/rtc-pcf85053.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 047d242faf68..ca441affa186 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18692,6 +18692,13 @@ S: Maintained
F: Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
F: sound/soc/codecs/tfa989x.c
+NXP RTC PCF85053 DRIVER
+M: Pankit Gargi <pankit.garg@nxp.com>
+M: Lakshay Piplani <lakshay.piplani@nxp.com>
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: drivers/rtc/rtc-pcf85053.c
+
NZXT-KRAKEN2 HARDWARE MONITORING DRIVER
M: Jonas Malaco <jonas@protocubo.io>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 2933c41c77c8..e25b75d38849 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -994,6 +994,16 @@ config RTC_DRV_PCF85063
This driver can also be built as a module. If so, the module
will be called rtc-pcf85063.
+config RTC_DRV_PCF85053
+ tristate "NXP PCF85053"
+ depends on OF && I2C
+ help
+ If you say yes here you get support for the NXP PCF85053 I2C Bootable CPU RTC
+ chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-pcf85053.
+
config RTC_DRV_RV3029C2
tristate "Micro Crystal RV3029/3049"
depends on RTC_I2C_AND_SPI
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 8221bda6e6dc..90c4f73393af 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -129,6 +129,7 @@ obj-$(CONFIG_RTC_DRV_PCAP) += rtc-pcap.o
obj-$(CONFIG_RTC_DRV_PCF2123) += rtc-pcf2123.o
obj-$(CONFIG_RTC_DRV_PCF2127) += rtc-pcf2127.o
obj-$(CONFIG_RTC_DRV_PCF85063) += rtc-pcf85063.o
+obj-$(CONFIG_RTC_DRV_PCF85053) += rtc-pcf85053.o
obj-$(CONFIG_RTC_DRV_PCF8523) += rtc-pcf8523.o
obj-$(CONFIG_RTC_DRV_PCF85363) += rtc-pcf85363.o
obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o
diff --git a/drivers/rtc/rtc-pcf85053.c b/drivers/rtc/rtc-pcf85053.c
new file mode 100644
index 000000000000..5829b0e7a67a
--- /dev/null
+++ b/drivers/rtc/rtc-pcf85053.c
@@ -0,0 +1,717 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2025 NXP
+
+#include <linux/bcd.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/rtc.h>
+#include <linux/slab.h>
+#include <linux/pm_wakeirq.h>
+#include <linux/regmap.h>
+
+#define PCF85053_REG_SC 0x00 /* seconds */
+#define PCF85053_REG_SCA 0x01 /* alarm */
+#define PCF85053_REG_MN 0x02 /* minutes */
+#define PCF85053_REG_MNA 0x03 /* alarm */
+#define PCF85053_REG_HR 0x04 /* hour */
+#define PCF85053_REG_HRA 0x05 /* alarm */
+#define PCF85053_REG_DW 0x06 /* day of week */
+#define PCF85053_REG_DM 0x07 /* day of month */
+#define PCF85053_REG_MO 0x08 /* month */
+#define PCF85053_REG_YR 0x09 /* year */
+#define PCF85053_REG_CTRL 0x0A /* timer control */
+#define PCF85053_REG_ST 0x0B /* status */
+#define PCF85053_REG_CLKO 0x0C /* clock out */
+#define PCF85053_REG_ACC 0x14 /* xclk access */
+
+#define PCF85053_BIT_AF BIT(7)
+#define PCF85053_BIT_ST BIT(7)
+#define PCF85053_BIT_DM BIT(6)
+#define PCF85053_BIT_HF BIT(5)
+#define PCF85053_BIT_DSM BIT(4)
+#define PCF85053_BIT_AIE BIT(3)
+#define PCF85053_BIT_OFIE BIT(2)
+#define PCF85053_BIT_CIE BIT(1)
+#define PCF85053_BIT_TWO BIT(0)
+#define PCF85053_BIT_XCLK BIT(7)
+
+#define PCF85053_REG_BAT_MASK 0x07 /* Battery mask */
+#define PCF85053A_BVL_MASK 0x07
+#define PCF85053A_BVL_LOW_THRESHOLD 0x02
+#define PCF85053_REG_CLKO_F_MASK 0x03 /* Frequenc mask */
+#define PCF85053_REG_CLKO_CKE 0x80 /* clock out enabled */
+#define PCF85053_BIT_OF BIT(6)
+
+#define PCF85053_HR_PM BIT(7)
+#define PCF85053_HR_24H_MASK GENMASK(5, 0)
+
+struct pcf85053_config {
+ const struct regmap_config regmap;
+ unsigned has_alarms:1;
+};
+
+struct pcf85053 {
+ struct rtc_device *rtc;
+ struct regmap *regmap;
+#ifdef CONFIG_COMMON_CLK
+ struct clk_hw clkout_hw;
+#endif
+ bool is_primary;
+};
+
+static inline int pcf85053_read_two_bit(struct pcf85053 *pcf85053, bool *two)
+{
+ unsigned int ctrl;
+ int err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
+ if (err)
+ return err;
+
+ *two = !!(ctrl & PCF85053_BIT_TWO);
+
+ return 0;
+}
+
+static inline bool pcf85053_time_write_access(struct pcf85053 *pcf85053)
+{
+ bool two;
+
+ if (pcf85053_read_two_bit(pcf85053, &two))
+ return false;
+
+ /* Primary writes iff TWO=1; secondary writes iff TWO=0 */
+ return pcf85053->is_primary ? two : !two;
+}
+
+static int pcf85053_set_alarm_mode(struct regmap *regmap, bool on)
+{
+ unsigned int val;
+ int err;
+
+ val = on ? PCF85053_BIT_AIE : 0;
+
+ err = regmap_update_bits(regmap, PCF85053_REG_CTRL,
+ PCF85053_BIT_AIE,
+ val);
+ if (err)
+ return err;
+
+ return regmap_update_bits(regmap, PCF85053_REG_ST,
+ PCF85053_BIT_AF, 0);
+}
+
+static int pcf85053_get_alarm_mode(struct device *dev,
+ unsigned char *alarm_enable, unsigned char *alarm_flag)
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ unsigned int val;
+ int err;
+
+ if (alarm_enable) {
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &val);
+ if (err)
+ return err;
+
+ *alarm_enable = val & PCF85053_BIT_AIE;
+ }
+
+ if (alarm_flag) {
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_ST, &val);
+ if (err)
+ return err;
+
+ *alarm_flag = val & PCF85053_BIT_AF;
+ }
+
+ return 0;
+}
+
+static irqreturn_t pcf85053_irq(int irq, void *dev_id)
+{
+ struct device *dev = dev_id;
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ bool changed;
+ int err;
+
+ err = regmap_update_bits_check(pcf85053->regmap,
+ PCF85053_REG_ST,
+ PCF85053_BIT_AF, 0,
+ &changed);
+
+ if (err || !changed)
+ return IRQ_NONE;
+
+ rtc_update_irq(pcf85053->rtc, 1, RTC_IRQF | RTC_AF);
+ return IRQ_HANDLED;
+}
+
+/*
+ * In the routines that deal directly with the PCF85053 hardware, we use
+ * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
+ */
+static int pcf85053_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ unsigned int ctrl, st, h12;
+ bool is_24h, is_bin;
+ u8 regs[10], hr;
+ int err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
+ if (err)
+ return err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_ST, &st);
+ if (err)
+ return err;
+
+ if (ctrl & PCF85053_BIT_ST)
+ return -EINVAL;
+
+ err = regmap_bulk_read(pcf85053->regmap, PCF85053_REG_SC, regs, sizeof(regs));
+ if (err)
+ return err;
+
+ if (ctrl & PCF85053_BIT_DM) {
+ tm->tm_sec = regs[PCF85053_REG_SC] & 0x7F;
+ tm->tm_min = regs[PCF85053_REG_MN] & 0x7F;
+ tm->tm_mday = regs[PCF85053_REG_DM] & 0x3F;
+ tm->tm_mon = (regs[PCF85053_REG_MO] & 0x1F) - 1;
+ tm->tm_year = regs[PCF85053_REG_YR] + 100;
+ } else {
+ tm->tm_sec = bcd2bin(regs[PCF85053_REG_SC] & 0x7F);
+ tm->tm_min = bcd2bin(regs[PCF85053_REG_MN] & 0x7F);
+ tm->tm_mday = bcd2bin(regs[PCF85053_REG_DM] & 0x3F);
+ tm->tm_mon = bcd2bin(regs[PCF85053_REG_MO] & 0x1F) - 1;
+ tm->tm_year = bcd2bin(regs[PCF85053_REG_YR]) + 100;
+ }
+ tm->tm_wday = regs[PCF85053_REG_DW] & 0x07;
+
+ hr = regs[PCF85053_REG_HR];
+ is_24h = ctrl & PCF85053_BIT_HF;
+ is_bin = ctrl & PCF85053_BIT_DM;
+
+ if (is_24h) {
+ tm->tm_hour = is_bin
+ ? (hr & PCF85053_HR_24H_MASK)
+ : bcd2bin(hr & PCF85053_HR_24H_MASK);
+ } else {
+ h12 = is_bin ? (hr & PCF85053_HR_24H_MASK)
+ : bcd2bin(hr & PCF85053_HR_24H_MASK);
+
+ tm->tm_hour = (h12 == 12) ? ((hr & PCF85053_HR_PM) ? 12 : 0) :
+ ((hr & PCF85053_HR_PM) ? h12 + 12 : h12);
+ }
+
+ return 0;
+}
+
+static int pcf85053_rtc_set_time(struct device *dev, struct rtc_time *tm)
+
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ unsigned int ctrl;
+ int err, ret;
+ u8 buf[10];
+
+ /*
+ * By default, secondary have write access to time registers as TWO
+ * bit is 0 by default, if we set nxp,interface = "primary" and the
+ * nxp,write-access in device tree, then TWO bits gets set and primary
+ * gets write access to time registers.
+ */
+ if (!pcf85053_time_write_access(pcf85053))
+ return -EACCES;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
+ if (err)
+ return err;
+
+ /*
+ * HF = 1, 24-hour mode
+ * DM = 1, binary (not BCD)
+ */
+ if (!(ctrl & PCF85053_BIT_HF) ||
+ !(ctrl & PCF85053_BIT_DM)) {
+ err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_CTRL,
+ PCF85053_BIT_HF | PCF85053_BIT_DM,
+ PCF85053_BIT_HF | PCF85053_BIT_DM);
+ if (err)
+ return err;
+ }
+
+ buf[0] = tm->tm_sec & 0x7F;
+ buf[1] = 0;
+ buf[2] = tm->tm_min & 0x7F;
+ buf[3] = 0;
+ buf[4] = tm->tm_hour & PCF85053_HR_24H_MASK;
+ buf[5] = 0;
+ buf[6] = tm->tm_wday & 0x07;
+ buf[7] = tm->tm_mday & 0x3F;
+ buf[8] = (tm->tm_mon + 1) & 0x1F;
+ buf[9] = (tm->tm_year - 100) & 0xFF;
+
+ if (pcf85053->is_primary) {
+ err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_CTRL,
+ PCF85053_BIT_ST, PCF85053_BIT_ST);
+ if (err)
+ return err;
+
+ ret = regmap_bulk_write(pcf85053->regmap, PCF85053_REG_SC, buf, sizeof(buf));
+ err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_CTRL,
+ PCF85053_BIT_ST, 0);
+ return ret ? ret : err;
+ }
+
+ return regmap_bulk_write(pcf85053->regmap, PCF85053_REG_SC, buf, sizeof(buf));
+}
+
+static int pcf85053_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *tm)
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ unsigned int ctrl, h12;
+ bool is_24h, is_bin, pm;
+ u8 buf[5];
+ u8 hr;
+ int err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
+ if (err)
+ return err;
+
+ err = regmap_bulk_read(pcf85053->regmap, PCF85053_REG_SCA, buf, sizeof(buf));
+ if (err)
+ return err;
+
+ if (ctrl & PCF85053_BIT_DM) {
+ tm->time.tm_sec = buf[0] & 0x7F; /* SCA */
+ tm->time.tm_min = buf[2] & 0x7F; /* MNA */
+ } else {
+ tm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
+ tm->time.tm_min = bcd2bin(buf[2] & 0x7F);
+ }
+
+ hr = buf[4];
+ is_24h = !!(ctrl & PCF85053_BIT_HF);
+ is_bin = !!(ctrl & PCF85053_BIT_DM);
+
+ if (is_24h) {
+ tm->time.tm_hour = is_bin
+ ? (hr & PCF85053_HR_24H_MASK)
+ : bcd2bin(hr & PCF85053_HR_24H_MASK);
+ } else {
+ pm = !!(hr & PCF85053_HR_PM);
+
+ if (is_bin)
+ h12 = (hr & PCF85053_HR_24H_MASK);
+ else
+ h12 = (bcd2bin(hr & PCF85053_HR_24H_MASK));
+
+ if (h12 == 12)
+ h12 = 0;
+ tm->time.tm_hour = pm ? (h12 + 12) : h12;
+ }
+
+ return pcf85053_get_alarm_mode(dev, &tm->enabled, &tm->pending);
+}
+
+static int pcf85053_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *tm)
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ unsigned int ctrl;
+ u8 sec, min, hr;
+ int err;
+
+ /*
+ * Only primary can set alarm, as secondary have read only access
+ * to alarm, control and status registers
+ */
+ if (!pcf85053->is_primary)
+ return -EACCES;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
+ if (err)
+ return err;
+
+ /*
+ * HF = 1, 24-hour mode
+ * DM = 1, binary (not BCD)
+ */
+ if (!(ctrl & PCF85053_BIT_HF) ||
+ !(ctrl & PCF85053_BIT_DM)) {
+ err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_CTRL,
+ PCF85053_BIT_HF | PCF85053_BIT_DM,
+ PCF85053_BIT_HF | PCF85053_BIT_DM);
+ if (err)
+ return err;
+ }
+
+ err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_ST,
+ PCF85053_BIT_AF, 0);
+ if (err)
+ return err;
+
+ sec = tm->time.tm_sec & 0x7F;
+ min = tm->time.tm_min & 0x7F;
+ hr = tm->time.tm_hour & PCF85053_HR_24H_MASK;
+
+ err = regmap_write(pcf85053->regmap, PCF85053_REG_SCA, sec);
+ if (err)
+ return err;
+
+ err = regmap_write(pcf85053->regmap, PCF85053_REG_MNA, min);
+ if (err)
+ return err;
+
+ err = regmap_write(pcf85053->regmap, PCF85053_REG_HRA, hr);
+ if (err)
+ return err;
+
+ return pcf85053_set_alarm_mode(pcf85053->regmap, tm->enabled);
+}
+
+static int pcf85053_irq_enable(struct device *dev, unsigned int enabled)
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "%s: alarm enable=%d\n", __func__, enabled);
+
+ return pcf85053_set_alarm_mode(pcf85053->regmap, enabled);
+}
+
+static int pcf85053_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
+{
+ struct pcf85053 *pcf85053 = dev_get_drvdata(dev);
+ unsigned int val = 0, vl_status = 0;
+ unsigned int bvl;
+ int status;
+
+ switch (cmd) {
+ case RTC_VL_READ:
+ status = regmap_read(pcf85053->regmap, PCF85053_REG_ST, &val);
+ if (status)
+ return status;
+
+ if (val & PCF85053_BIT_OF)
+ vl_status |= RTC_VL_DATA_INVALID;
+
+ bvl = val & PCF85053A_BVL_MASK;
+
+ if (bvl == 0x00)
+ vl_status |= RTC_VL_BACKUP_EMPTY;
+ else if (bvl <= PCF85053A_BVL_LOW_THRESHOLD)
+ vl_status |= RTC_VL_BACKUP_LOW;
+
+ return put_user(vl_status, (unsigned int __user *)arg);
+
+ default:
+ return -ENOIOCTLCMD;
+ }
+}
+
+#ifdef CONFIG_COMMON_CLK
+/*
+ * Handling of the clkout
+ */
+
+#define clkout_hw_to_pcf85053(_hw) container_of(_hw, struct pcf85053, clkout_hw)
+
+static const int clkout_rates[] = {
+ 32768,
+ 1024,
+ 32,
+ 1,
+};
+
+static unsigned long pcf85053_clkout_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct pcf85053 *pcf85053 = clkout_hw_to_pcf85053(hw);
+ unsigned int val = 0;
+ int err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CLKO, &val);
+ if (err)
+ return 0;
+
+ val &= PCF85053_REG_CLKO_F_MASK;
+ return clkout_rates[val];
+}
+
+static int pcf85053_clkout_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ int i;
+ unsigned long best = 0;
+
+ for (i = 0; i < ARRAY_SIZE(clkout_rates); i++) {
+ if (clkout_rates[i] <= req->rate) {
+ best = clkout_rates[i];
+ break;
+ }
+ }
+ if (!best)
+ best = clkout_rates[ARRAY_SIZE(clkout_rates) - 1];
+
+ req->rate = best;
+ return 0;
+}
+
+static int pcf85053_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct pcf85053 *pcf85053 = clkout_hw_to_pcf85053(hw);
+ unsigned int val = 0;
+ int err, i;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CLKO, &val);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
+ if (clkout_rates[i] == rate) {
+ val &= ~PCF85053_REG_CLKO_F_MASK;
+ val |= i;
+ return regmap_write(pcf85053->regmap, PCF85053_REG_CLKO, val);
+ }
+
+ return -EINVAL;
+}
+
+static int pcf85053_clkout_control(struct clk_hw *hw, bool enable)
+{
+ struct pcf85053 *pcf85053 = clkout_hw_to_pcf85053(hw);
+ unsigned int val = 0;
+ int err;
+
+ if (!pcf85053->is_primary)
+ return -EACCES;
+
+ val = PCF85053_BIT_XCLK;
+ err = regmap_write(pcf85053->regmap, PCF85053_REG_ACC, val);
+ if (err)
+ return err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CLKO, &val);
+ if (err)
+ return err;
+
+ if (enable)
+ val |= PCF85053_REG_CLKO_CKE;
+ else
+ val &= ~PCF85053_REG_CLKO_CKE;
+
+ return regmap_write(pcf85053->regmap, PCF85053_REG_CLKO, val);
+}
+
+static int pcf85053_clkout_prepare(struct clk_hw *hw)
+{
+ return pcf85053_clkout_control(hw, 1);
+}
+
+static void pcf85053_clkout_unprepare(struct clk_hw *hw)
+{
+ pcf85053_clkout_control(hw, 0);
+}
+
+static int pcf85053_clkout_is_prepared(struct clk_hw *hw)
+{
+ struct pcf85053 *pcf85053 = clkout_hw_to_pcf85053(hw);
+ unsigned int val = 0;
+ int err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CLKO, &val);
+ if (err)
+ return err;
+
+ return val & PCF85053_REG_CLKO_CKE;
+}
+
+static const struct clk_ops pcf85053_clkout_ops = {
+ .prepare = pcf85053_clkout_prepare,
+ .unprepare = pcf85053_clkout_unprepare,
+ .is_prepared = pcf85053_clkout_is_prepared,
+ .recalc_rate = pcf85053_clkout_recalc_rate,
+ .determine_rate = pcf85053_clkout_determine_rate,
+ .set_rate = pcf85053_clkout_set_rate,
+};
+
+static struct clk *pcf85053_clkout_register_clk(struct pcf85053 *pcf85053)
+{
+ struct device *dev = pcf85053->rtc->dev.parent;
+ struct device_node *node = dev->of_node;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ init.name = "pcf85053-clkout";
+ init.ops = &pcf85053_clkout_ops;
+ init.flags = 0;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+ pcf85053->clkout_hw.init = &init;
+
+ /* optional override of the clockname */
+ of_property_read_string(node, "clock-output-names", &init.name);
+
+ /* register the clock */
+ clk = devm_clk_register(dev, &pcf85053->clkout_hw);
+
+ if (!IS_ERR(clk))
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+ return clk;
+}
+#endif
+
+static const struct rtc_class_ops pcf85053_rtc_ops = {
+ .read_time = pcf85053_rtc_read_time,
+ .set_time = pcf85053_rtc_set_time,
+ .read_alarm = pcf85053_rtc_read_alarm,
+ .set_alarm = pcf85053_rtc_set_alarm,
+ .alarm_irq_enable = pcf85053_irq_enable,
+ .ioctl = pcf85053_ioctl,
+};
+
+static const struct pcf85053_config config_pcf85053 = {
+ .regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x1D,
+ },
+ .has_alarms = 1,
+};
+
+static int pcf85053_probe(struct i2c_client *client)
+{
+ const struct pcf85053_config *config;
+ struct device *dev = &client->dev;
+ const char *iface = NULL;
+ struct pcf85053 *pcf85053;
+ int err;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
+ I2C_FUNC_SMBUS_BYTE |
+ I2C_FUNC_SMBUS_BLOCK_DATA))
+ return -ENODEV;
+
+ pcf85053 = devm_kzalloc(dev, sizeof(struct pcf85053),
+ GFP_KERNEL);
+ if (!pcf85053)
+ return -ENOMEM;
+
+ config = i2c_get_match_data(client);
+ if (!config)
+ return -ENODEV;
+
+ pcf85053->regmap = devm_regmap_init_i2c(client, &config->regmap);
+ if (IS_ERR(pcf85053->regmap))
+ return PTR_ERR(pcf85053->regmap);
+
+ dev_set_drvdata(dev, pcf85053);
+
+ pcf85053->is_primary = true;
+
+ if (of_property_read_string(dev->of_node, "nxp,interface", &iface))
+ return dev_err_probe(dev, -EINVAL,
+ "Missing mandatory property: nxp,interface\n");
+ if (!strcmp(iface, "primary"))
+ pcf85053->is_primary = true;
+ else if (!strcmp(iface, "secondary"))
+ pcf85053->is_primary = false;
+ else
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid value for nxp,interface: %s\n", iface);
+
+ if (pcf85053->is_primary) {
+ unsigned int ctrl;
+ int err;
+
+ err = regmap_read(pcf85053->regmap, PCF85053_REG_CTRL, &ctrl);
+ if (err)
+ return err;
+
+ if (of_property_read_bool(dev->of_node, "nxp,write-access")) {
+ if (!(ctrl & PCF85053_BIT_TWO)) {
+ err = regmap_update_bits(pcf85053->regmap, PCF85053_REG_CTRL,
+ PCF85053_BIT_TWO, PCF85053_BIT_TWO);
+ if (err)
+ return err;
+ }
+ dev_dbg(dev, "Ownership set: TWO=1 (primary writes)\n");
+ } else {
+ /* TWO (Time Write Ownership) bit defaults to 0 (Secondary) */
+ dev_dbg(dev, "Default ownership set: TWO=0 (secondary writes)\n");
+ }
+ }
+
+ pcf85053->rtc = devm_rtc_allocate_device(dev);
+ if (IS_ERR(pcf85053->rtc))
+ return PTR_ERR(pcf85053->rtc);
+
+ /*
+ * The year register stores 00-99 and the RTC treats any value where
+ * (year % 4) == 0 as a leap year, with no special handling for the
+ * centuries. Mapping 00-99 to 2000-2099 keeps the leap-year logic
+ * correct over the whole usable range.
+ */
+ pcf85053->rtc->ops = &pcf85053_rtc_ops;
+ pcf85053->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
+ pcf85053->rtc->range_max = RTC_TIMESTAMP_END_2099;
+ clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85053->rtc->features);
+ clear_bit(RTC_FEATURE_ALARM, pcf85053->rtc->features);
+
+ if (config->has_alarms && client->irq > 0) {
+ err = devm_request_threaded_irq(dev, client->irq,
+ NULL, pcf85053_irq,
+ IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
+ "pcf85053", dev);
+ if (err) {
+ dev_err(dev, "unable to request IRQ %d\n", client->irq);
+ } else {
+ set_bit(RTC_FEATURE_ALARM, pcf85053->rtc->features);
+ devm_device_init_wakeup(dev);
+ err = dev_pm_set_wake_irq(dev, client->irq);
+ if (err)
+ dev_err(dev, "failed to enable irq wake\n");
+ }
+ }
+
+#ifdef CONFIG_COMMON_CLK
+ /* register clk in common clk framework */
+ pcf85053_clkout_register_clk(pcf85053);
+#endif
+
+ return devm_rtc_register_device(pcf85053->rtc);
+}
+
+static const struct i2c_device_id pcf85053_id[] = {
+ { "pcf85053", .driver_data = (kernel_ulong_t)&config_pcf85053 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, pcf85053_id);
+
+static const struct of_device_id pcf85053_of_match[] = {
+ { .compatible = "nxp,pcf85053", .data = &config_pcf85053 },
+ {}
+};
+MODULE_DEVICE_TABLE(of, pcf85053_of_match);
+
+static struct i2c_driver pcf85053_driver = {
+ .driver = {
+ .name = "rtc-pcf85053",
+ .of_match_table = of_match_ptr(pcf85053_of_match),
+ },
+ .probe = pcf85053_probe,
+ .id_table = pcf85053_id,
+};
+
+module_i2c_driver(pcf85053_driver);
+
+MODULE_AUTHOR("Pankit Garg <pankit.garg@nxp.com>");
+MODULE_AUTHOR("Lakshay Piplani <lakshay.piplani@nxp.com>");
+MODULE_DESCRIPTION("NXP pcf85053 RTC driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v7 1/2] dt-bindings: rtc: Add pcf85053 support
From: Lakshay Piplani @ 2025-11-27 12:04 UTC (permalink / raw)
To: alexandre.belloni, linux-rtc, linux-kernel, robh, krzk+dt,
conor+dt, devicetree
Cc: vikash.bansal, priyanka.jain, shashank.rebbapragada,
Lakshay Piplani, Pankit Garg, Conor Dooley
Add device tree bindings for NXP PCF85053 RTC chip.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Lakshay Piplani <lakshay.piplani@nxp.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
V6 -> V7: - no changes
- Added Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
V5 -> V6: - Dropped driver-specific commentary from property descriptions.
- Simplified and clarified descriptions for better readability.
V4 -> V5: - Updated schema validation logic to enforce correct combinations of
'nxp,interface' and 'nxp,write-access' using oneOf clauses.
- Refined property descriptions for clarity and hardware alignment.
V3 -> V4: Add dedicated nxp,pcf85053.yaml.
Remove entry from trivial-rtc.yaml.
V2 -> V3: Moved MAINTAINERS file changes to the driver patch
V1 -> V2: Handled dt-bindings by trivial-rtc.yaml
.../devicetree/bindings/rtc/nxp,pcf85053.yaml | 114 ++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85053.yaml
diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85053.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf85053.yaml
new file mode 100644
index 000000000000..81cfceabc04c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85053.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2025 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nxp,pcf85053.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PCF85053 Real Time Clock
+
+maintainers:
+ - Pankit Garg <pankit.garg@nxp.com>
+ - Lakshay Piplani <lakshay.piplani@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - nxp,pcf85053
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ nxp,interface:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ primary, secondary ]
+ description: |
+ Identifies this host's logical role in a multi-host topology for the
+ PCF85053 RTC. The device exposes a "TWO" ownership bit in the CTRL
+ register that gates which host may write time/alarm registers.
+ - "primary": Designated host that *may* claim write ownership (set
+ CTRL.TWO=1) **if** write-access is explicitly requested.
+ - "secondary": Peer host that writes only when CTRL.TWO=0 (default).
+
+ This property determines the intended role of the host in relation to
+ the write ownership.
+
+ The actual role depends on whether 'nxp,write-access' is also specified.
+ Supported configurations are:-
+ 1. Primary with 'nxp,write-access' -> primary claims write ownership.
+ 2. Primary without 'nxp,write-access' -> primary is ready only; secondary may write.
+ 3. Secondary (must not specify 'nxp,write-access') -> Secondary writes only
+ when no primary claims ownership.
+
+ nxp,write-access:
+ type: boolean
+ description: |
+ Indicates that write ownership of the PCF85053 RTC should be claimed by setting
+ CTRL.TWO=1. This property is only valid when acting as the primary interface
+ (nxp,interface="primary").
+
+required:
+ - compatible
+ - reg
+ - nxp,interface
+
+additionalProperties: false
+
+allOf:
+ - $ref: rtc.yaml#
+ - if:
+ properties:
+ nxp,interface:
+ const: secondary
+ then:
+ not:
+ required: [ "nxp,write-access" ]
+
+examples:
+ # Single host example.
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6f {
+ compatible = "nxp,pcf85053";
+ reg = <0x6f>;
+ nxp,interface = "primary";
+ nxp,write-access;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ # Dual-host example: one primary that claims writes; one secondary that never claims writes.
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6f {
+ compatible = "nxp,pcf85053";
+ reg = <0x6f>;
+ nxp,interface = "primary";
+ nxp,write-access;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6f {
+ compatible = "nxp,pcf85053";
+ reg = <0x6f>;
+ nxp,interface = "secondary";
+ };
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH v6 17/17] MAINTAINERS: Add ROHM BD72720 PMIC
From: Matti Vaittinen @ 2025-11-27 11:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1022 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
Add the ROHM BD72720 PMIC driver files to be maintained by undersigned.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
Revision history:
RFCv1 =>:
- No changes
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe01aa31c58b..7e3c1eac7cda 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22353,6 +22353,7 @@ S: Supported
F: drivers/clk/clk-bd718x7.c
F: drivers/gpio/gpio-bd71815.c
F: drivers/gpio/gpio-bd71828.c
+F: drivers/gpio/gpio-bd72720.c
F: drivers/mfd/rohm-bd71828.c
F: drivers/mfd/rohm-bd718x7.c
F: drivers/mfd/rohm-bd9576.c
@@ -22369,6 +22370,7 @@ F: drivers/watchdog/bd96801_wdt.c
F: include/linux/mfd/rohm-bd71815.h
F: include/linux/mfd/rohm-bd71828.h
F: include/linux/mfd/rohm-bd718x7.h
+F: include/linux/mfd/rohm-bd72720.h
F: include/linux/mfd/rohm-bd957x.h
F: include/linux/mfd/rohm-bd96801.h
F: include/linux/mfd/rohm-bd96802.h
--
2.52.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v6 16/17] power: supply: bd71828-power: Support ROHM BD72720
From: Matti Vaittinen @ 2025-11-27 11:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 11744 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The ROHM BD72720 is a power management IC with a charger and coulomb
counter block which is closely related to the charger / coulomb counter
found from the BD71815, BD71828, BD71879 which are all supported by the
bd71828-power driver. Due to the similarities it makes sense to support
also the BD72720 with the same driver.
Add basic support for the charger logic on ROHM BD72720.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
Revision history:
v2 => :
- No changes
RFCv1 => v2:
- Support using 9-bit register addresses (offset of 0x100) with the
BD72720
- Simplify probe and IC data as we don't need two regmaps
- Drop two BD72720 specific functions as we no longer need different
regmap for it.
Note: This patch depends on the series: "power: supply: add charger for
BD71828" by Andreas:
https://lore.kernel.org/all/20250918-bd71828-charger-v5-0-851164839c28@kemnade.info/
NOTE: Fuel-gauging is not supported. You can find an unmaintained
downstream reference-driver with a fuel-gauge example from:
https://github.com/RohmSemiconductor/Linux-Kernel-PMIC-Drivers/releases/tag/bd72720-reference-driver-v1
---
drivers/power/supply/bd71828-power.c | 134 +++++++++++++++++++++++----
1 file changed, 116 insertions(+), 18 deletions(-)
diff --git a/drivers/power/supply/bd71828-power.c b/drivers/power/supply/bd71828-power.c
index ce73c0f48397..438e220a9cb7 100644
--- a/drivers/power/supply/bd71828-power.c
+++ b/drivers/power/supply/bd71828-power.c
@@ -5,6 +5,7 @@
#include <linux/kernel.h>
#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
+#include <linux/mfd/rohm-bd72720.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
@@ -51,12 +52,14 @@ struct pwr_regs {
unsigned int chg_state;
unsigned int bat_temp;
unsigned int dcin_stat;
+ unsigned int dcin_online_mask;
unsigned int dcin_collapse_limit;
unsigned int chg_set1;
unsigned int chg_en;
unsigned int vbat_alm_limit_u;
unsigned int conf;
unsigned int vdcin;
+ unsigned int vdcin_himask;
};
static const struct pwr_regs pwr_regs_bd71828 = {
@@ -67,12 +70,14 @@ static const struct pwr_regs pwr_regs_bd71828 = {
.chg_state = BD71828_REG_CHG_STATE,
.bat_temp = BD71828_REG_BAT_TEMP,
.dcin_stat = BD71828_REG_DCIN_STAT,
+ .dcin_online_mask = BD7182x_MASK_DCIN_DET,
.dcin_collapse_limit = BD71828_REG_DCIN_CLPS,
.chg_set1 = BD71828_REG_CHG_SET1,
.chg_en = BD71828_REG_CHG_EN,
.vbat_alm_limit_u = BD71828_REG_ALM_VBAT_LIMIT_U,
.conf = BD71828_REG_CONF,
.vdcin = BD71828_REG_VDCIN_U,
+ .vdcin_himask = BD7182x_MASK_VDCIN_U,
};
static const struct pwr_regs pwr_regs_bd71815 = {
@@ -85,6 +90,7 @@ static const struct pwr_regs pwr_regs_bd71815 = {
.chg_state = BD71815_REG_CHG_STATE,
.bat_temp = BD71815_REG_BAT_TEMP,
.dcin_stat = BD71815_REG_DCIN_STAT,
+ .dcin_online_mask = BD7182x_MASK_DCIN_DET,
.dcin_collapse_limit = BD71815_REG_DCIN_CLPS,
.chg_set1 = BD71815_REG_CHG_SET1,
.chg_en = BD71815_REG_CHG_SET1,
@@ -92,6 +98,31 @@ static const struct pwr_regs pwr_regs_bd71815 = {
.conf = BD71815_REG_CONF,
.vdcin = BD71815_REG_VM_DCIN_U,
+ .vdcin_himask = BD7182x_MASK_VDCIN_U,
+};
+
+static struct pwr_regs pwr_regs_bd72720 = {
+ .vbat_avg = BD72720_REG_VM_SA_VBAT_U,
+ .ibat = BD72720_REG_CC_CURCD_U,
+ .ibat_avg = BD72720_REG_CC_SA_CURCD_U,
+ .btemp_vth = BD72720_REG_VM_BTMP_U,
+ /*
+ * Note, state 0x40 IMP_CHK. not documented
+ * on other variants but was still handled in
+ * existing code. No memory traces as to why.
+ */
+ .chg_state = BD72720_REG_CHG_STATE,
+ .bat_temp = BD72720_REG_CHG_BAT_TEMP_STAT,
+ .dcin_stat = BD72720_REG_INT_VBUS_SRC,
+ .dcin_online_mask = BD72720_MASK_DCIN_DET,
+ .dcin_collapse_limit = -1, /* Automatic. Setting not supported */
+ .chg_set1 = BD72720_REG_CHG_SET_1,
+ .chg_en = BD72720_REG_CHG_EN,
+ /* 15mV note in data-sheet */
+ .vbat_alm_limit_u = BD72720_REG_ALM_VBAT_TH_U,
+ .conf = BD72720_REG_CONF, /* o XSTB, only PON. Seprate slave addr */
+ .vdcin = BD72720_REG_VM_VBUS_U, /* 10 bits not 11 as with other ICs */
+ .vdcin_himask = BD72720_MASK_VDCIN_U,
};
struct bd71828_power {
@@ -298,7 +329,7 @@ static int get_chg_online(struct bd71828_power *pwr, int *chg_online)
dev_err(pwr->dev, "Failed to read DCIN status\n");
return ret;
}
- *chg_online = ((r & BD7182x_MASK_DCIN_DET) != 0);
+ *chg_online = ((r & pwr->regs->dcin_online_mask) != 0);
return 0;
}
@@ -329,8 +360,8 @@ static int bd71828_bat_inserted(struct bd71828_power *pwr)
ret = val & BD7182x_MASK_CONF_PON;
if (ret)
- regmap_update_bits(pwr->regmap, pwr->regs->conf,
- BD7182x_MASK_CONF_PON, 0);
+ if (regmap_update_bits(pwr->regmap, pwr->regs->conf, BD7182x_MASK_CONF_PON, 0))
+ dev_err(pwr->dev, "Failed to write CONF register\n");
return ret;
}
@@ -358,11 +389,13 @@ static int bd71828_init_hardware(struct bd71828_power *pwr)
int ret;
/* TODO: Collapse limit should come from device-tree ? */
- ret = regmap_write(pwr->regmap, pwr->regs->dcin_collapse_limit,
- BD7182x_DCIN_COLLAPSE_DEFAULT);
- if (ret) {
- dev_err(pwr->dev, "Failed to write DCIN collapse limit\n");
- return ret;
+ if (pwr->regs->dcin_collapse_limit != (unsigned int)-1) {
+ ret = regmap_write(pwr->regmap, pwr->regs->dcin_collapse_limit,
+ BD7182x_DCIN_COLLAPSE_DEFAULT);
+ if (ret) {
+ dev_err(pwr->dev, "Failed to write DCIN collapse limit\n");
+ return ret;
+ }
}
ret = pwr->bat_inserted(pwr);
@@ -419,7 +452,7 @@ static int bd71828_charger_get_property(struct power_supply *psy,
break;
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
ret = bd7182x_read16_himask(pwr, pwr->regs->vdcin,
- BD7182x_MASK_VDCIN_U, &tmp);
+ pwr->regs->vdcin_himask, &tmp);
if (ret)
return ret;
@@ -630,6 +663,9 @@ BD_ISR_AC(dcin_ovp_det, "DCIN OVER VOLTAGE", true)
BD_ISR_DUMMY(dcin_mon_det, "DCIN voltage below threshold")
BD_ISR_DUMMY(dcin_mon_res, "DCIN voltage above threshold")
+BD_ISR_DUMMY(vbus_curr_limit, "VBUS current limited")
+BD_ISR_DUMMY(vsys_ov_res, "VSYS over-voltage cleared")
+BD_ISR_DUMMY(vsys_ov_det, "VSYS over-voltage")
BD_ISR_DUMMY(vsys_uv_res, "VSYS under-voltage cleared")
BD_ISR_DUMMY(vsys_uv_det, "VSYS under-voltage")
BD_ISR_DUMMY(vsys_low_res, "'VSYS low' cleared")
@@ -878,6 +914,51 @@ static int bd7182x_get_irqs(struct platform_device *pdev,
BDIRQ("bd71828-temp-125-over", bd71828_temp_vf125_det),
BDIRQ("bd71828-temp-125-under", bd71828_temp_vf125_res),
};
+ static const struct bd7182x_irq_res bd72720_irqs[] = {
+ BDIRQ("bd72720_int_vbus_rmv", BD_ISR_NAME(dcin_removed)),
+ BDIRQ("bd72720_int_vbus_det", bd7182x_dcin_detected),
+ BDIRQ("bd72720_int_vbus_mon_res", BD_ISR_NAME(dcin_mon_res)),
+ BDIRQ("bd72720_int_vbus_mon_det", BD_ISR_NAME(dcin_mon_det)),
+ BDIRQ("bd72720_int_vsys_mon_res", BD_ISR_NAME(vsys_mon_res)),
+ BDIRQ("bd72720_int_vsys_mon_det", BD_ISR_NAME(vsys_mon_det)),
+ BDIRQ("bd72720_int_vsys_uv_res", BD_ISR_NAME(vsys_uv_res)),
+ BDIRQ("bd72720_int_vsys_uv_det", BD_ISR_NAME(vsys_uv_det)),
+ BDIRQ("bd72720_int_vsys_lo_res", BD_ISR_NAME(vsys_low_res)),
+ BDIRQ("bd72720_int_vsys_lo_det", BD_ISR_NAME(vsys_low_det)),
+ BDIRQ("bd72720_int_vsys_ov_res", BD_ISR_NAME(vsys_ov_res)),
+ BDIRQ("bd72720_int_vsys_ov_det", BD_ISR_NAME(vsys_ov_det)),
+ BDIRQ("bd72720_int_bat_ilim", BD_ISR_NAME(vbus_curr_limit)),
+ BDIRQ("bd72720_int_chg_done", bd718x7_chg_done),
+ BDIRQ("bd72720_int_extemp_tout", BD_ISR_NAME(chg_wdg_temp)),
+ BDIRQ("bd72720_int_chg_wdt_exp", BD_ISR_NAME(chg_wdg)),
+ BDIRQ("bd72720_int_bat_mnt_out", BD_ISR_NAME(rechg_res)),
+ BDIRQ("bd72720_int_bat_mnt_in", BD_ISR_NAME(rechg_det)),
+ BDIRQ("bd72720_int_chg_trns", BD_ISR_NAME(chg_state_changed)),
+
+ BDIRQ("bd72720_int_vbat_mon_res", BD_ISR_NAME(bat_mon_res)),
+ BDIRQ("bd72720_int_vbat_mon_det", BD_ISR_NAME(bat_mon)),
+ BDIRQ("bd72720_int_vbat_sht_res", BD_ISR_NAME(bat_short_res)),
+ BDIRQ("bd72720_int_vbat_sht_det", BD_ISR_NAME(bat_short)),
+ BDIRQ("bd72720_int_vbat_lo_res", BD_ISR_NAME(bat_low_res)),
+ BDIRQ("bd72720_int_vbat_lo_det", BD_ISR_NAME(bat_low)),
+ BDIRQ("bd72720_int_vbat_ov_res", BD_ISR_NAME(bat_ov_res)),
+ BDIRQ("bd72720_int_vbat_ov_det", BD_ISR_NAME(bat_ov)),
+ BDIRQ("bd72720_int_bat_rmv", BD_ISR_NAME(bat_removed)),
+ BDIRQ("bd72720_int_bat_det", BD_ISR_NAME(bat_det)),
+ BDIRQ("bd72720_int_dbat_det", BD_ISR_NAME(bat_dead)),
+ BDIRQ("bd72720_int_bat_temp_trns", BD_ISR_NAME(temp_transit)),
+ BDIRQ("bd72720_int_lobtmp_res", BD_ISR_NAME(temp_bat_low_res)),
+ BDIRQ("bd72720_int_lobtmp_det", BD_ISR_NAME(temp_bat_low)),
+ BDIRQ("bd72720_int_ovbtmp_res", BD_ISR_NAME(temp_bat_hi_res)),
+ BDIRQ("bd72720_int_ovbtmp_det", BD_ISR_NAME(temp_bat_hi)),
+ BDIRQ("bd72720_int_ocur1_res", BD_ISR_NAME(bat_oc1_res)),
+ BDIRQ("bd72720_int_ocur1_det", BD_ISR_NAME(bat_oc1)),
+ BDIRQ("bd72720_int_ocur2_res", BD_ISR_NAME(bat_oc2_res)),
+ BDIRQ("bd72720_int_ocur2_det", BD_ISR_NAME(bat_oc2)),
+ BDIRQ("bd72720_int_ocur3_res", BD_ISR_NAME(bat_oc3_res)),
+ BDIRQ("bd72720_int_ocur3_det", BD_ISR_NAME(bat_oc3)),
+ BDIRQ("bd72720_int_cc_mon2_det", BD_ISR_NAME(bat_cc_mon)),
+ };
int num_irqs;
const struct bd7182x_irq_res *irqs;
@@ -890,6 +971,10 @@ static int bd7182x_get_irqs(struct platform_device *pdev,
irqs = &bd71815_irqs[0];
num_irqs = ARRAY_SIZE(bd71815_irqs);
break;
+ case ROHM_CHIP_TYPE_BD72720:
+ irqs = &bd72720_irqs[0];
+ num_irqs = ARRAY_SIZE(bd72720_irqs);
+ break;
default:
return -EINVAL;
}
@@ -958,21 +1043,27 @@ static int bd71828_power_probe(struct platform_device *pdev)
struct power_supply_config ac_cfg = {};
struct power_supply_config bat_cfg = {};
int ret;
- struct regmap *regmap;
-
- regmap = dev_get_regmap(pdev->dev.parent, NULL);
- if (!regmap) {
- dev_err(&pdev->dev, "No parent regmap\n");
- return -EINVAL;
- }
pwr = devm_kzalloc(&pdev->dev, sizeof(*pwr), GFP_KERNEL);
if (!pwr)
return -ENOMEM;
- pwr->regmap = regmap;
- pwr->dev = &pdev->dev;
+ /*
+ * The BD72720 MFD device registers two regmaps. Power-supply driver
+ * uses the "wrap-map", which provides access to both of the I2C slave
+ * addresses used by the BD72720
+ */
pwr->chip_type = platform_get_device_id(pdev)->driver_data;
+ if (pwr->chip_type != ROHM_CHIP_TYPE_BD72720)
+ pwr->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ else
+ pwr->regmap = dev_get_regmap(pdev->dev.parent, "wrap-map");
+ if (!pwr->regmap) {
+ dev_err(&pdev->dev, "No parent regmap\n");
+ return -EINVAL;
+ }
+
+ pwr->dev = &pdev->dev;
switch (pwr->chip_type) {
case ROHM_CHIP_TYPE_BD71828:
@@ -985,6 +1076,12 @@ static int bd71828_power_probe(struct platform_device *pdev)
pwr->get_temp = bd71815_get_temp;
pwr->regs = &pwr_regs_bd71815;
break;
+ case ROHM_CHIP_TYPE_BD72720:
+ pwr->bat_inserted = bd71828_bat_inserted;
+ pwr->regs = &pwr_regs_bd72720;
+ pwr->get_temp = bd71828_get_temp;
+ dev_dbg(pwr->dev, "Found ROHM BD72720\n");
+ break;
default:
dev_err(pwr->dev, "Unknown PMIC\n");
return -EINVAL;
@@ -1030,6 +1127,7 @@ static int bd71828_power_probe(struct platform_device *pdev)
static const struct platform_device_id bd71828_charger_id[] = {
{ "bd71815-power", ROHM_CHIP_TYPE_BD71815 },
{ "bd71828-power", ROHM_CHIP_TYPE_BD71828 },
+ { "bd72720-power", ROHM_CHIP_TYPE_BD72720 },
{ },
};
MODULE_DEVICE_TABLE(platform, bd71828_charger_id);
--
2.52.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v6 15/17] power: supply: bd71828: Support wider register addresses
From: Matti Vaittinen @ 2025-11-27 11:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2492 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The BD71828 power-supply driver assumes register addresses to be 8-bit.
The new BD72720 will use stacked register maps to hide paging which is
done using secondary I2C slave address. This requires use of 9-bit
register addresses in the power-supply driver (added offset 0x100 to
the 8-bit hardware register addresses).
The cost is slightly used memory consumption as the members in the
struct pwr_regs will be changed from u8 to unsigned int, which means 3
byte increase / member / instance.
This is currently 14 members (expected to possibly be increased when
adding new variants / new functionality which may introduce new
registers, but not expected to grow much) and 2 instances (will be 3
instances when BD72720 gets added).
So, even if the number of registers grew to 50 it'd be 150 bytes /
instance. Assuming we eventually supported 5 variants, it'd be
5 * 150 bytes, which stays very reasonable considering systems we are
dealing with.
As a side note, we can reduce the "wasted space / member / instance" from
3 bytes to 1 byte, by using u16 instead of the unsigned int if needed. I
rather use unsigned int to be initially prepared for devices with 32 bit
registers if there is no need to count bytes.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
---
Revision history:
v2 => :
- No changes
RFCv1 => v2:
- New patch
---
drivers/power/supply/bd71828-power.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/power/supply/bd71828-power.c b/drivers/power/supply/bd71828-power.c
index f667baedeb77..ce73c0f48397 100644
--- a/drivers/power/supply/bd71828-power.c
+++ b/drivers/power/supply/bd71828-power.c
@@ -44,19 +44,19 @@
#define VBAT_LOW_TH 0x00D4
struct pwr_regs {
- u8 vbat_avg;
- u8 ibat;
- u8 ibat_avg;
- u8 btemp_vth;
- u8 chg_state;
- u8 bat_temp;
- u8 dcin_stat;
- u8 dcin_collapse_limit;
- u8 chg_set1;
- u8 chg_en;
- u8 vbat_alm_limit_u;
- u8 conf;
- u8 vdcin;
+ unsigned int vbat_avg;
+ unsigned int ibat;
+ unsigned int ibat_avg;
+ unsigned int btemp_vth;
+ unsigned int chg_state;
+ unsigned int bat_temp;
+ unsigned int dcin_stat;
+ unsigned int dcin_collapse_limit;
+ unsigned int chg_set1;
+ unsigned int chg_en;
+ unsigned int vbat_alm_limit_u;
+ unsigned int conf;
+ unsigned int vdcin;
};
static const struct pwr_regs pwr_regs_bd71828 = {
--
2.52.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v6 14/17] rtc: bd70528: Support BD72720 rtc
From: Matti Vaittinen @ 2025-11-27 11:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3329 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The BD72720 has similar RTC block as a few other ROHM PMICs.
Add support for BD72720 RTC.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
Revision history:
RFCv1 =>:
- No changes
---
drivers/rtc/Kconfig | 3 ++-
drivers/rtc/rtc-bd70528.c | 21 ++++++++++++++-------
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 2933c41c77c8..418f6c28847a 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -561,7 +561,8 @@ config RTC_DRV_BD70528
depends on MFD_ROHM_BD71828
help
If you say Y here you will get support for the RTC
- block on ROHM BD71815 and BD71828 Power Management IC.
+ block on ROHM BD71815, BD71828 and BD72720 Power
+ Management ICs.
This driver can also be built as a module. If so, the module
will be called rtc-bd70528.
diff --git a/drivers/rtc/rtc-bd70528.c b/drivers/rtc/rtc-bd70528.c
index 954ac4ef53e8..4c8599761b2e 100644
--- a/drivers/rtc/rtc-bd70528.c
+++ b/drivers/rtc/rtc-bd70528.c
@@ -7,6 +7,7 @@
#include <linux/bcd.h>
#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
+#include <linux/mfd/rohm-bd72720.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -262,13 +263,13 @@ static int bd70528_probe(struct platform_device *pdev)
/*
* See also BD718XX_ALM_EN_OFFSET:
- * This works for BD71828 and BD71815 as they have same offset
- * between ALM0 start and ALM0_MASK. If new ICs are to be
- * added this requires proper check as ALM0_MASK is not located
- * at the end of ALM0 block - but after all ALM blocks so if
- * amount of ALMs differ the offset to enable/disable is likely
- * to be incorrect and enable/disable must be given as own
- * reg address here.
+ * This works for BD71828, BD71815, and BD72720 as they all
+ * have same offset between the ALM0 start and the ALM0_MASK.
+ * If new ICs are to be added this requires proper check as
+ * the ALM0_MASK is not located at the end of ALM0 block -
+ * but after all ALM blocks. If amount of ALMs differ, the
+ * offset to enable/disable is likely to be incorrect and
+ * enable/disable must be given as own reg address here.
*/
bd_rtc->bd718xx_alm_block_start = BD71815_REG_RTC_ALM_START;
hour_reg = BD71815_REG_HOUR;
@@ -278,6 +279,11 @@ static int bd70528_probe(struct platform_device *pdev)
bd_rtc->bd718xx_alm_block_start = BD71828_REG_RTC_ALM_START;
hour_reg = BD71828_REG_RTC_HOUR;
break;
+ case ROHM_CHIP_TYPE_BD72720:
+ bd_rtc->reg_time_start = BD72720_REG_RTC_START;
+ bd_rtc->bd718xx_alm_block_start = BD72720_REG_RTC_ALM_START;
+ hour_reg = BD72720_REG_RTC_HOUR;
+ break;
default:
dev_err(&pdev->dev, "Unknown chip\n");
return -ENOENT;
@@ -337,6 +343,7 @@ static int bd70528_probe(struct platform_device *pdev)
static const struct platform_device_id bd718x7_rtc_id[] = {
{ "bd71828-rtc", ROHM_CHIP_TYPE_BD71828 },
{ "bd71815-rtc", ROHM_CHIP_TYPE_BD71815 },
+ { "bd72720-rtc", ROHM_CHIP_TYPE_BD72720 },
{ },
};
MODULE_DEVICE_TABLE(platform, bd718x7_rtc_id);
--
2.52.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v6 13/17] clk: clk-bd718x7: Support BD72720 clk gate
From: Matti Vaittinen @ 2025-11-27 11:20 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2578 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The BD72720 has similar simple clk gate as a few other ROHM PMICs.
Add support for BD72720 clk gate.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
Revision history:
RFCv1 =>:
- No changes
---
drivers/clk/Kconfig | 4 ++--
drivers/clk/clk-bd718x7.c | 10 ++++++++--
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3a1611008e48..619bd63a3c77 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -475,8 +475,8 @@ config COMMON_CLK_BD718XX
tristate "Clock driver for 32K clk gates on ROHM PMICs"
depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
help
- This driver supports ROHM BD71837, BD71847, BD71850, BD71815
- and BD71828 PMICs clock gates.
+ This driver supports ROHM BD71837, BD71847, BD71850, BD71815,
+ BD71828, and BD72720 PMICs clock gates.
config COMMON_CLK_FIXED_MMIO
bool "Clock driver for Memory Mapped Fixed values"
diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c
index ac40b669d60b..1cae974e6d1d 100644
--- a/drivers/clk/clk-bd718x7.c
+++ b/drivers/clk/clk-bd718x7.c
@@ -19,7 +19,8 @@
#define BD71828_REG_OUT32K 0x4B
/* BD71837 and BD71847 */
#define BD718XX_REG_OUT32K 0x2E
-
+/* BD72720 */
+#define BD72720_REG_OUT32K 0x9a
/*
* BD71837, BD71847, and BD71828 all use bit [0] to clk output control
*/
@@ -118,6 +119,10 @@ static int bd71837_clk_probe(struct platform_device *pdev)
c->reg = BD71815_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
break;
+ case ROHM_CHIP_TYPE_BD72720:
+ c->reg = BD72720_REG_OUT32K;
+ c->mask = CLK_OUT_EN_MASK;
+ break;
default:
dev_err(&pdev->dev, "Unknown clk chip\n");
return -EINVAL;
@@ -146,6 +151,7 @@ static const struct platform_device_id bd718x7_clk_id[] = {
{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
{ "bd71815-clk", ROHM_CHIP_TYPE_BD71815 },
+ { "bd72720-clk", ROHM_CHIP_TYPE_BD72720 },
{ },
};
MODULE_DEVICE_TABLE(platform, bd718x7_clk_id);
@@ -161,6 +167,6 @@ static struct platform_driver bd71837_clk = {
module_platform_driver(bd71837_clk);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
-MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver");
+MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and BD72720 chip clk driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd718xx-clk");
--
2.52.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v6 12/17] gpio: Support ROHM BD72720 gpios
From: Matti Vaittinen @ 2025-11-27 11:19 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 10901 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
The ROHM BD72720 has 6 pins which may be configured as GPIOs. The
GPIO1 ... GPIO5 and EPDEN pins. The configuration is done to OTP at the
manufacturing, and it can't be read at runtime. The device-tree is
required to tell the software which of the pins are used as GPIOs.
Keep the pin mapping static regardless the OTP. This way the user-space
can always access the BASE+N for GPIO(N+1) (N = 0 to 4), and BASE + 5
for the EPDEN pin. Do this by setting always the number of GPIOs to 6,
and by using the valid-mask to invalidate the pins which aren't configured
as GPIOs.
First two pins can be set to be either input or output by OTP. Direction
can't be changed by software. Rest of the pins can be set as outputs
only. All of the pins support generating interrupts.
Support the Input/Output state getting/setting and the output mode
configuration (open-drain/push-pull).
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
Revision history:
RFCv1 => :
- No changes
---
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-bd72720.c | 281 ++++++++++++++++++++++++++++++++++++
3 files changed, 291 insertions(+)
create mode 100644 drivers/gpio/gpio-bd72720.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7ee3afbc2b05..0c612c5163c5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1319,6 +1319,15 @@ config GPIO_BD71828
This driver can also be built as a module. If so, the module
will be called gpio-bd71828.
+config GPIO_BD72720
+ tristate "ROHM BD72720 and BD73900 PMIC GPIO support"
+ depends on MFD_ROHM_BD71828
+ help
+ Support for GPIO on ROHM BD72720 and BD73900 PMICs. There are two
+ pins which can be configured to GPI or GPO, and three pins which can
+ be configured to GPO on the ROHM PMIC. The pin configuration is done
+ on OTP at manufacturing.
+
config GPIO_BD9571MWV
tristate "ROHM BD9571 GPIO support"
depends on MFD_BD9571MWV
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ec296fa14bfd..7a5d03db3021 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o
obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o
obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o
+obj-$(CONFIG_GPIO_BD72720) += gpio-bd72720.o
obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o
obj-$(CONFIG_GPIO_BLZP1600) += gpio-blzp1600.o
obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
diff --git a/drivers/gpio/gpio-bd72720.c b/drivers/gpio/gpio-bd72720.c
new file mode 100644
index 000000000000..6549dbf4c7ad
--- /dev/null
+++ b/drivers/gpio/gpio-bd72720.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support to GPIOs on ROHM BD72720 and BD79300
+ * Copyright 2025 ROHM Semiconductors.
+ * Author: Matti Vaittinen <mazziesaccount@gmail.com>
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/rohm-bd72720.h>
+
+#define BD72720_GPIO_OPEN_DRAIN 0
+#define BD72720_GPIO_CMOS BIT(1)
+#define BD72720_INT_GPIO1_IN_SRC 4
+/*
+ * The BD72720 has several "one time programmable" (OTP) configurations which
+ * can be set at manufacturing phase. A set of these options allow using pins
+ * as GPIO. The OTP configuration can't be read at run-time, so drivers rely on
+ * device-tree to advertise the correct options.
+ *
+ * Both DVS[0,1] pins can be configured to be used for:
+ * - OTP0: regulator RUN state control
+ * - OTP1: GPI
+ * - OTP2: GPO
+ * - OTP3: Power sequencer output
+ * Data-sheet also states that these PINs can always be used for IRQ but the
+ * driver limits this by allowing them to be used for IRQs with OTP1 only.
+ *
+ * Pins GPIO_EXTEN0 (GPIO3), GPIO_EXTEN1 (GPIO4), GPIO_FAULT_B (GPIO5) have OTP
+ * options for a specific (non GPIO) purposes, but also an option to configure
+ * them to be used as a GPO.
+ *
+ * OTP settings can be separately configured for each pin.
+ *
+ * DT properties:
+ * "rohm,pin-dvs0" and "rohm,pin-dvs1" can be set to one of the values:
+ * "dvs-input", "gpi", "gpo".
+ *
+ * "rohm,pin-exten0", "rohm,pin-exten1" and "rohm,pin-fault_b" can be set to:
+ * "gpo"
+ */
+
+enum bd72720_gpio_state {
+ BD72720_PIN_UNKNOWN,
+ BD72720_PIN_GPI,
+ BD72720_PIN_GPO,
+};
+
+enum {
+ BD72720_GPIO1,
+ BD72720_GPIO2,
+ BD72720_GPIO3,
+ BD72720_GPIO4,
+ BD72720_GPIO5,
+ BD72720_GPIO_EPDEN,
+ BD72720_NUM_GPIOS
+};
+
+struct bd72720_gpio {
+ /* chip.parent points the MFD which provides DT node and regmap */
+ struct gpio_chip chip;
+ /* dev points to the platform device for devm and prints */
+ struct device *dev;
+ struct regmap *regmap;
+ int gpio_is_input;
+};
+
+static int bd72720gpi_get(struct bd72720_gpio *bdgpio, unsigned int reg_offset)
+{
+ int ret, val, shift;
+
+ ret = regmap_read(bdgpio->regmap, BD72720_REG_INT_ETC1_SRC, &val);
+ if (ret)
+ return ret;
+
+ shift = BD72720_INT_GPIO1_IN_SRC + reg_offset;
+
+ return (val >> shift) & 1;
+}
+
+static int bd72720gpo_get(struct bd72720_gpio *bdgpio,
+ unsigned int offset)
+{
+ const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
+ BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
+ int ret, val;
+
+ ret = regmap_read(bdgpio->regmap, regs[offset], &val);
+ if (ret)
+ return ret;
+
+ return val & BD72720_GPIO_HIGH;
+}
+
+static int bd72720gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+
+ if (BIT(offset) & bdgpio->gpio_is_input)
+ return bd72720gpi_get(bdgpio, offset);
+
+ return bd72720gpo_get(bdgpio, offset);
+}
+
+static int bd72720gpo_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+ const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
+ BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
+
+ if (BIT(offset) & bdgpio->gpio_is_input) {
+ dev_dbg(bdgpio->dev, "pin %d not output.\n", offset);
+ return -EINVAL;
+ }
+
+ if (value)
+ return regmap_set_bits(bdgpio->regmap, regs[offset],
+ BD72720_GPIO_HIGH);
+
+ return regmap_clear_bits(bdgpio->regmap, regs[offset],
+ BD72720_GPIO_HIGH);
+}
+
+static int bd72720_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+ const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
+ BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
+ BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
+
+ /*
+ * We can only set the output mode, which makes sense only when output
+ * OTP configuration is used.
+ */
+ if (BIT(offset) & bdgpio->gpio_is_input)
+ return -ENOTSUPP;
+
+ switch (pinconf_to_config_param(config)) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ return regmap_update_bits(bdgpio->regmap,
+ regs[offset],
+ BD72720_GPIO_DRIVE_MASK,
+ BD72720_GPIO_OPEN_DRAIN);
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ return regmap_update_bits(bdgpio->regmap,
+ regs[offset],
+ BD72720_GPIO_DRIVE_MASK,
+ BD72720_GPIO_CMOS);
+ default:
+ break;
+ }
+
+ return -ENOTSUPP;
+}
+
+static int bd72720gpo_direction_get(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
+
+ if (BIT(offset) & bdgpio->gpio_is_input)
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int bd72720_valid_mask(struct gpio_chip *gc,
+ unsigned long *valid_mask,
+ unsigned int ngpios)
+{
+ static const char * const properties[] = {
+ "rohm,pin-dvs0", "rohm,pin-dvs1", "rohm,pin-exten0",
+ "rohm,pin-exten1", "rohm,pin-fault_b"
+ };
+ struct bd72720_gpio *g = gpiochip_get_data(gc);
+ const char *val;
+ int i, ret;
+
+ *valid_mask = BIT(BD72720_GPIO_EPDEN);
+
+ if (!gc->parent)
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ ret = fwnode_property_read_string(dev_fwnode(gc->parent),
+ properties[i], &val);
+
+ if (ret) {
+ if (ret == -EINVAL)
+ continue;
+
+ dev_err(g->dev, "pin %d (%s), bad configuration\n", i,
+ properties[i]);
+
+ return ret;
+ }
+
+ if (strcmp(val, "gpi") == 0) {
+ if (i != BD72720_GPIO1 && i != BD72720_GPIO2) {
+ dev_warn(g->dev,
+ "pin %d (%s) does not support INPUT mode",
+ i, properties[i]);
+ continue;
+ }
+
+ *valid_mask |= BIT(i);
+ g->gpio_is_input |= BIT(i);
+ } else if (strcmp(val, "gpo") == 0) {
+ *valid_mask |= BIT(i);
+ }
+ }
+
+ return 0;
+}
+
+/* Template for GPIO chip */
+static const struct gpio_chip bd72720gpo_chip = {
+ .label = "bd72720",
+ .owner = THIS_MODULE,
+ .get = bd72720gpio_get,
+ .get_direction = bd72720gpo_direction_get,
+ .set = bd72720gpo_set,
+ .set_config = bd72720_gpio_set_config,
+ .init_valid_mask = bd72720_valid_mask,
+ .can_sleep = true,
+ .ngpio = BD72720_NUM_GPIOS,
+ .base = -1,
+};
+
+static int gpo_bd72720_probe(struct platform_device *pdev)
+{
+ struct bd72720_gpio *g;
+ struct device *parent, *dev;
+
+ /*
+ * Bind devm lifetime to this platform device => use dev for devm.
+ * also the prints should originate from this device.
+ */
+ dev = &pdev->dev;
+ /* The device-tree and regmap come from MFD => use parent for that */
+ parent = dev->parent;
+
+ g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+ if (!g)
+ return -ENOMEM;
+
+ g->chip = bd72720gpo_chip;
+ g->dev = dev;
+ g->chip.parent = parent;
+ g->regmap = dev_get_regmap(parent, NULL);
+
+ return devm_gpiochip_add_data(dev, &g->chip, g);
+}
+
+static const struct platform_device_id bd72720_gpio_id[] = {
+ { "bd72720-gpio" },
+ { },
+};
+MODULE_DEVICE_TABLE(platform, bd72720_gpio_id);
+
+static struct platform_driver gpo_bd72720_driver = {
+ .driver = {
+ .name = "bd72720-gpio",
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = gpo_bd72720_probe,
+ .id_table = bd72720_gpio_id,
+};
+module_platform_driver(gpo_bd72720_driver);
+
+MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
+MODULE_DESCRIPTION("GPIO interface for BD72720 and BD73900");
+MODULE_LICENSE("GPL");
--
2.52.0
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply related
* [PATCH v6 11/17] regulator: bd71828: Support ROHM BD72720
From: Matti Vaittinen @ 2025-11-27 11:19 UTC (permalink / raw)
To: Matti Vaittinen, Matti Vaittinen
Cc: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sebastian Reichel, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Matti Vaittinen, Linus Walleij,
Bartosz Golaszewski, Alexandre Belloni, linux-leds, devicetree,
linux-kernel, linux-pm, linux-clk, linux-gpio, linux-rtc,
Andreas Kemnade
In-Reply-To: <cover.1764241265.git.mazziesaccount@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 40951 bytes --]
From: Matti Vaittinen <mazziesaccount@gmail.com>
ROHM BD72720 is a power management IC which integrates 10 buck and 11 LDO
regulators. This PMIC has plenty of commonalities with the BD71828 and
BD71879.
The BD72720 does also have similar 'run-level'-concept as the BD71828 had.
It allows controlling the regulator's 'en masse', although only BUCK1
and LDO1 can utilize this in BD72720. Similar to BD71828, this 'en
masse' -control is not supported by this driver.
Support the voltage and enable/disable state control for the BD72720.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
---
Revision history:
v3 =>:
- No changes
v2 => v3:
- The ldon-head dt-property was changed to microvolts. Adapt the driver
to that
RFCv1 => v2:
- No changes
There are some new variants planned. Most notably, the BD73900 should be
similar to the BD72720 what comes to the regulator control logic.
If the run-level control is needed, there are some downstream extensions
available at:
https://rohmsemiconductor.github.io/Linux-Kernel-PMIC-Drivers/BD72720/
---
drivers/regulator/Kconfig | 8 +-
drivers/regulator/bd71828-regulator.c | 993 +++++++++++++++++++++++++-
2 files changed, 992 insertions(+), 9 deletions(-)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index d84f3d054c59..660863f096e3 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -241,13 +241,13 @@ config REGULATOR_BD71815
will be called bd71815-regulator.
config REGULATOR_BD71828
- tristate "ROHM BD71828 Power Regulator"
+ tristate "ROHM BD71828, BD72720 and BD73900 Power Regulators"
depends on MFD_ROHM_BD71828
select REGULATOR_ROHM
help
- This driver supports voltage regulators on ROHM BD71828 PMIC.
- This will enable support for the software controllable buck
- and LDO regulators.
+ This driver supports voltage regulators on ROHM BD71828,
+ BD71879, BD72720 and BD73900 PMICs. This will enable
+ support for the software controllable buck and LDO regulators.
This driver can also be built as a module. If so, the module
will be called bd71828-regulator.
diff --git a/drivers/regulator/bd71828-regulator.c b/drivers/regulator/bd71828-regulator.c
index 3d18dbfdb84e..ba16671ece42 100644
--- a/drivers/regulator/bd71828-regulator.c
+++ b/drivers/regulator/bd71828-regulator.c
@@ -3,12 +3,15 @@
// bd71828-regulator.c ROHM BD71828GW-DS1 regulator driver
//
+#include <linux/cleanup.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/rohm-bd71828.h>
+#include <linux/mfd/rohm-bd72720.h>
#include <linux/module.h>
+#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -16,6 +19,7 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
+#define BD72720_MASK_LDON_HEAD GENMASK(2, 0)
struct reg_init {
unsigned int reg;
unsigned int mask;
@@ -64,6 +68,26 @@ static const struct reg_init bd71828_buck7_inits[] = {
},
};
+#define BD72720_MASK_DVS_BUCK1_CTRL BIT(4)
+#define BD72720_MASK_DVS_LDO1_CTRL BIT(5)
+
+static const struct reg_init bd72720_buck1_inits[] = {
+ {
+ .reg = BD72720_REG_PS_CTRL_2,
+ .mask = BD72720_MASK_DVS_BUCK1_CTRL,
+ .val = 0, /* Disable "run-level" control */
+ },
+};
+
+static const struct reg_init bd72720_ldo1_inits[] = {
+ {
+ .reg = BD72720_REG_PS_CTRL_2,
+ .mask = BD72720_MASK_DVS_LDO1_CTRL,
+ .val = 0, /* Disable "run-level" control */
+ },
+};
+
+/* BD71828 Buck voltages */
static const struct linear_range bd71828_buck1267_volts[] = {
REGULATOR_LINEAR_RANGE(500000, 0x00, 0xef, 6250),
REGULATOR_LINEAR_RANGE(2000000, 0xf0, 0xff, 0),
@@ -84,13 +108,79 @@ static const struct linear_range bd71828_buck5_volts[] = {
REGULATOR_LINEAR_RANGE(3300000, 0x10, 0x1f, 0),
};
+/* BD71828 LDO voltages */
static const struct linear_range bd71828_ldo_volts[] = {
REGULATOR_LINEAR_RANGE(800000, 0x00, 0x31, 50000),
REGULATOR_LINEAR_RANGE(3300000, 0x32, 0x3f, 0),
};
+/* BD72720 Buck voltages */
+static const struct linear_range bd72720_buck1234_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0xc0, 6250),
+ REGULATOR_LINEAR_RANGE(1700000, 0xc1, 0xff, 0),
+};
+
+static const struct linear_range bd72720_buck589_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0x78, 10000),
+ REGULATOR_LINEAR_RANGE(1700000, 0x79, 0xff, 0),
+};
+
+static const struct linear_range bd72720_buck67_volts[] = {
+ REGULATOR_LINEAR_RANGE(1500000, 0x00, 0xb4, 10000),
+ REGULATOR_LINEAR_RANGE(3300000, 0xb5, 0xff, 0),
+};
+
+/*
+ * The BUCK10 on BD72720 has two modes of operation, depending on a LDON_HEAD
+ * setting. When LDON_HEAD is 0x0, the behaviour is as with other bucks, eg.
+ * voltage can be set to a values indicated below using the VSEL register.
+ *
+ * However, when LDON_HEAD is set to 0x1 ... 0x7, BUCK 10 voltage is, according
+ * to the data-sheet, "automatically adjusted following LDON_HEAD setting and
+ * clamped to BUCK10_VID setting".
+ *
+ * Again, reading the data-sheet shows a "typical connection" where the BUCK10
+ * is used to supply the LDOs 1-4. My assumption is that in practice, this
+ * means that the BUCK10 voltage will be adjusted based on the maximum output
+ * of the LDO 1-4 (to minimize power loss). This makes sense.
+ *
+ * Auto-adjusting regulators aren't something I really like to model in the
+ * driver though - and, if the auto-adjustment works as intended, then there
+ * should really be no need to software to care about the buck10 voltages.
+ * If enable/disable control is still needed, we can implement buck10 as a
+ * regulator with only the enable/disable ops - and device-tree can be used
+ * to model the supply-relations. I believe this could allow the regulator
+ * framework to automagically disable the BUCK10 if all LDOs that are being
+ * supplied by it are disabled.
+ */
+static const struct linear_range bd72720_buck10_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0xc0, 6250),
+ REGULATOR_LINEAR_RANGE(1700000, 0xc1, 0xff, 0),
+};
+
+/* BD72720 LDO voltages */
+static const struct linear_range bd72720_ldo1234_volts[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0x00, 0x50, 6250),
+ REGULATOR_LINEAR_RANGE(1000000, 0x51, 0x7f, 0),
+};
+
+static const struct linear_range bd72720_ldo57891011_volts[] = {
+ REGULATOR_LINEAR_RANGE(750000, 0x00, 0xff, 10000),
+};
+
+static const struct linear_range bd72720_ldo6_volts[] = {
+ REGULATOR_LINEAR_RANGE(600000, 0x00, 0x78, 10000),
+ REGULATOR_LINEAR_RANGE(1800000, 0x79, 0x7f, 0),
+};
+
static const unsigned int bd71828_ramp_delay[] = { 2500, 5000, 10000, 20000 };
+/*
+ * BD72720 supports setting both the ramp-up and ramp-down values
+ * separately. Do we need to support ramp-down setting?
+ */
+static const unsigned int bd72720_ramp_delay[] = { 5000, 7500, 10000, 12500 };
+
static int buck_set_hw_dvs_levels(struct device_node *np,
const struct regulator_desc *desc,
struct regulator_config *cfg)
@@ -171,6 +261,24 @@ static const struct regulator_ops bd71828_ldo6_ops = {
.is_enabled = regulator_is_enabled_regmap,
};
+static const struct regulator_ops bd72720_regulator_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
+};
+
+static const struct regulator_ops bd72720_buck10_ldon_head_op = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
+};
+
static const struct bd71828_regulator_data bd71828_rdata[] = {
{
.desc = {
@@ -677,22 +785,890 @@ static const struct bd71828_regulator_data bd71828_rdata[] = {
},
};
+#define BD72720_BUCK10_DESC_INDEX 10
+#define BD72720_NUM_BUCK_VOLTS 0x100
+#define BD72720_NUM_LDO_VOLTS 0x100
+#define BD72720_NUM_LDO12346_VOLTS 0x80
+
+static const struct bd71828_regulator_data bd72720_rdata[] = {
+ {
+ .desc = {
+ .name = "buck1",
+ .of_match = of_match_ptr("buck1"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK1,
+ .type = REGULATOR_VOLTAGE,
+
+ /*
+ * The BD72720 BUCK1 and LDO1 support GPIO toggled
+ * sub-RUN states called RUN0, RUN1, RUN2 and RUN3.
+ * The "operating mode" (sub-RUN states or normal)
+ * can be changed by a register.
+ *
+ * When the sub-RUN states are used, the voltage and
+ * enable state depend on a state specific
+ * configuration. The voltage and enable configuration
+ * for BUCK1 and LDO1 can be defined for each sub-RUN
+ * state using BD72720_REG_[BUCK,LDO]1_VSEL_R[0,1,2,3]
+ * voltage selection registers and the bits
+ * BD72720_MASK_RUN_[0,1,2,3]_EN in the enable registers.
+ * The PMIC will change both the BUCK1 and LDO1 voltages
+ * to the states defined in these registers when
+ * "DVS GPIOs" are toggled.
+ *
+ * If RUN 0 .. RUN 4 states are to be used, the normal
+ * voltage configuration mechanisms do not apply
+ * and we should overwrite the ops and ignore the
+ * voltage setting/getting registers which are setup
+ * here. This is not supported for now. If you need
+ * this functionality, you may try merging functionality
+ * from a downstream driver:
+ * https://rohmsemiconductor.github.io/Linux-Kernel-PMIC-Drivers/BD72720/
+ */
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK1_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK1_VSEL_RB,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK1_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR, /* Deep idle in data-sheet */
+ .run_reg = BD72720_REG_BUCK1_VSEL_RB,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK1_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK1_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK1_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ .reg_inits = bd72720_buck1_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd72720_buck1_inits),
+ }, {
+ .desc = {
+ .name = "buck2",
+ .of_match = of_match_ptr("buck2"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK2,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK2_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK2_VSEL_R,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK2_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK2_VSEL_R,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK2_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK2_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK2_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck3",
+ .of_match = of_match_ptr("buck3"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK3,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK3_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK3_VSEL_R,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK3_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK3_VSEL_R,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK3_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK3_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK3_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck4",
+ .of_match = of_match_ptr("buck4"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK4,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck1234_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK4_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK4_VSEL_R,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK4_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK4_VSEL_R,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_reg = BD72720_REG_BUCK4_VSEL_I,
+ .idle_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_BUCK4_VSEL_S,
+ .suspend_mask = BD72720_MASK_BUCK_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_BUCK4_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_BUCK_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck5",
+ .of_match = of_match_ptr("buck5"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK5,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck589_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK5_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK5_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK5_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK5_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck6",
+ .of_match = of_match_ptr("buck6"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK6,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck67_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck67_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK6_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK6_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK6_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK6_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck7",
+ .of_match = of_match_ptr("buck7"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK7,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck67_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck67_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK7_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK7_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK7_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK7_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck8",
+ .of_match = of_match_ptr("buck8"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK8,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck589_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK8_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK8_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK8_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK8_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck9",
+ .of_match = of_match_ptr("buck9"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK9,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck589_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck589_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK9_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK9_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK9_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK9_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "buck10",
+ .of_match = of_match_ptr("buck10"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_BUCK10,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_buck10_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_buck10_volts),
+ .n_voltages = BD72720_NUM_BUCK_VOLTS,
+ .enable_reg = BD72720_REG_BUCK10_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_BUCK10_VSEL,
+ .vsel_mask = BD72720_MASK_BUCK_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_BUCK10_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_BUCK10_VSEL,
+ .run_mask = BD72720_MASK_BUCK_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo1",
+ .of_match = of_match_ptr("ldo1"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO1,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO1_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO1_VSEL_RB,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO1_MODE1,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO1_VSEL_RB,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO1_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO1_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO1_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ .reg_inits = bd72720_ldo1_inits,
+ .reg_init_amnt = ARRAY_SIZE(bd72720_ldo1_inits),
+ }, {
+ .desc = {
+ .name = "ldo2",
+ .of_match = of_match_ptr("ldo2"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO2,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO2_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO2_VSEL_R,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO2_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO2_VSEL_R,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO2_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO2_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO2_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo3",
+ .of_match = of_match_ptr("ldo3"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO3,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO3_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO3_VSEL_R,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO3_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO3_VSEL_R,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO3_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO3_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO3_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo4",
+ .of_match = of_match_ptr("ldo4"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO4,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo1234_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo1234_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO4_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO4_VSEL_R,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO4_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO4_VSEL_R,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_reg = BD72720_REG_LDO4_VSEL_I,
+ .idle_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_reg = BD72720_REG_LDO4_VSEL_S,
+ .suspend_mask = BD72720_MASK_LDO12346_VSEL,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_reg = BD72720_REG_LDO4_VSEL_DI,
+ .lpsr_mask = BD72720_MASK_LDO12346_VSEL,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo5",
+ .of_match = of_match_ptr("ldo5"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO5,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO5_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO5_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO5_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO5_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo6",
+ .of_match = of_match_ptr("ldo6"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO6,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo6_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo6_volts),
+ .n_voltages = BD72720_NUM_LDO12346_VOLTS,
+ .enable_reg = BD72720_REG_LDO6_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO6_VSEL,
+ .vsel_mask = BD72720_MASK_LDO12346_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO6_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO6_VSEL,
+ .run_mask = BD72720_MASK_LDO12346_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo7",
+ .of_match = of_match_ptr("ldo7"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO7,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO7_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO7_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO7_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO7_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo8",
+ .of_match = of_match_ptr("ldo8"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO8,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO8_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO8_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO8_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO8_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo9",
+ .of_match = of_match_ptr("ldo9"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO9,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO9_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO9_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO9_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO9_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo10",
+ .of_match = of_match_ptr("ldo10"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO10,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO10_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO10_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO10_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO10_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ }, {
+ .desc = {
+ .name = "ldo11",
+ .of_match = of_match_ptr("ldo11"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = BD72720_LDO11,
+ .type = REGULATOR_VOLTAGE,
+ .ops = &bd72720_regulator_ops,
+ .linear_ranges = bd72720_ldo57891011_volts,
+ .n_linear_ranges = ARRAY_SIZE(bd72720_ldo57891011_volts),
+ .n_voltages = BD72720_NUM_LDO_VOLTS,
+ .enable_reg = BD72720_REG_LDO11_ON,
+ .enable_mask = BD72720_MASK_RUN_B_EN,
+ .vsel_reg = BD72720_REG_LDO11_VSEL,
+ .vsel_mask = BD72720_MASK_LDO_VSEL,
+
+ .ramp_delay_table = bd72720_ramp_delay,
+ .n_ramp_values = ARRAY_SIZE(bd72720_ramp_delay),
+ .ramp_reg = BD72720_REG_LDO11_MODE,
+ .ramp_mask = BD72720_MASK_RAMP_UP_DELAY,
+ .owner = THIS_MODULE,
+ .of_parse_cb = buck_set_hw_dvs_levels,
+ },
+ .dvs = {
+ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE |
+ ROHM_DVS_LEVEL_SUSPEND |
+ ROHM_DVS_LEVEL_LPSR,
+ .run_reg = BD72720_REG_LDO11_VSEL,
+ .run_mask = BD72720_MASK_LDO_VSEL,
+ .idle_on_mask = BD72720_MASK_IDLE_EN,
+ .suspend_on_mask = BD72720_MASK_SUSPEND_EN,
+ .lpsr_on_mask = BD72720_MASK_DEEP_IDLE_EN,
+ },
+ },
+};
+
+static int bd72720_buck10_ldon_head_mode(struct device *dev,
+ struct device_node *npreg,
+ struct regmap *regmap,
+ struct regulator_desc *buck10_desc)
+{
+ struct device_node *np __free(device_node) =
+ of_get_child_by_name(npreg, "buck10");
+ uint32_t ldon_head;
+ int ldon_val;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "failed to find buck10 regulator node\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_read_u32(np, "rohm,ldon-head-microvolt", &ldon_head);
+ if (ret == -EINVAL)
+ return 0;
+ if (ret)
+ return ret;
+
+ /*
+ * LDON_HEAD mode means the BUCK10 is used to supply LDOs 1-4 and
+ * the BUCK 10 voltage is automatically set to follow LDO 1-4
+ * settings. Thus the BUCK10 should not allow voltage [g/s]etting.
+ */
+ buck10_desc->ops = &bd72720_buck10_ldon_head_op;
+
+ ldon_val = ldon_head / 50000 + 1;
+ if (ldon_head > 300000) {
+ dev_warn(dev, "Unsupported LDON_HEAD, clamping to 300 mV\n");
+ ldon_val = 7;
+ }
+
+ return regmap_update_bits(regmap, BD72720_REG_LDO1_MODE2,
+ BD72720_MASK_LDON_HEAD, ldon_val);
+}
+
+static int bd72720_dt_parse(struct device *dev,
+ struct regulator_desc *buck10_desc,
+ struct regmap *regmap)
+{
+ struct device_node *nproot __free(device_node) =
+ of_get_child_by_name(dev->parent->of_node, "regulators");
+
+ if (!nproot) {
+ dev_err(dev, "failed to find regulators node\n");
+ return -ENODEV;
+ }
+
+ return bd72720_buck10_ldon_head_mode(dev, nproot, regmap, buck10_desc);
+}
+
static int bd71828_probe(struct platform_device *pdev)
{
- int i, j, ret;
+ int i, j, ret, num_regulators;
struct regulator_config config = {
.dev = pdev->dev.parent,
};
+ enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;
+ struct bd71828_regulator_data *rdata;
config.regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!config.regmap)
return -ENODEV;
- for (i = 0; i < ARRAY_SIZE(bd71828_rdata); i++) {
+ switch (chip) {
+ case ROHM_CHIP_TYPE_BD72720:
+ rdata = devm_kmemdup(&pdev->dev, bd72720_rdata,
+ sizeof(bd72720_rdata), GFP_KERNEL);
+ if (!rdata)
+ return -ENOMEM;
+
+ ret = bd72720_dt_parse(&pdev->dev, &rdata[BD72720_BUCK10_DESC_INDEX].desc,
+ config.regmap);
+ if (ret)
+ return ret;
+
+ num_regulators = ARRAY_SIZE(bd72720_rdata);
+ break;
+
+ case ROHM_CHIP_TYPE_BD71828:
+ rdata = devm_kmemdup(&pdev->dev, bd71828_rdata,
+ sizeof(bd71828_rdata), GFP_KERNEL);
+ if (!rdata)
+ return -ENOMEM;
+
+ num_regulators = ARRAY_SIZE(bd71828_rdata);
+
+ break;
+ default:
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "Unsupported device\n");
+ }
+
+ for (i = 0; i < num_regulators; i++) {
struct regulator_dev *rdev;
- const struct bd71828_regulator_data *rd;
+ struct bd71828_regulator_data *rd;
+
+ rd = &rdata[i];
- rd = &bd71828_rdata[i];
+ config.driver_data = rd;
rdev = devm_regulator_register(&pdev->dev,
&rd->desc, &config);
if (IS_ERR(rdev))
@@ -714,12 +1690,20 @@ static int bd71828_probe(struct platform_device *pdev)
return 0;
}
+static const struct platform_device_id bd71828_pmic_id[] = {
+ { "bd71828-pmic", ROHM_CHIP_TYPE_BD71828 },
+ { "bd72720-pmic", ROHM_CHIP_TYPE_BD72720 },
+ { },
+};
+MODULE_DEVICE_TABLE(platform, bd71828_pmic_id);
+
static struct platform_driver bd71828_regulator = {
.driver = {
.name = "bd71828-pmic",
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = bd71828_probe,
+ .id_table = bd71828_pmic_id,
};
module_platform_driver(bd71828_regulator);
@@ -727,4 +1711,3 @@ module_platform_driver(bd71828_regulator);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("BD71828 voltage regulator driver");
MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bd71828-pmic");
--
2.52.0
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