From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Subject: Re: [PATCH v5 2/3] virtio_pci: Use the DMA API for virtqueues when possible Date: Wed, 17 Sep 2014 09:49:31 -0700 Message-ID: <1410972571.12562.24.camel@infradead.org> References: <6c31406005160303a7ee291a933c267f8e55fa85.1410931077.git.luto@amacapital.net> <1410955351.30672.27.camel@pasglop> <20140917141639.GA13684@redhat.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============6791659547471110543==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.linux-foundation.org Errors-To: virtualization-bounces@lists.linux-foundation.org List-Archive: List-Post: To: Andy Lutomirski Cc: "linux-s390@vger.kernel.org" , Konrad Rzeszutek Wilk , "Michael S. Tsirkin" , Benjamin Herrenschmidt , Linux Virtualization , Christian Borntraeger , "linux390@de.ibm.com" , Paolo Bonzini List-ID: --===============6791659547471110543== Content-Type: multipart/signed; micalg="sha-1"; protocol="application/x-pkcs7-signature"; boundary="=-6M6SbuO61NM4dJJLStt1" --=-6M6SbuO61NM4dJJLStt1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-09-17 at 09:07 -0700, Andy Lutomirski wrote: >=20 > I still think that this is a property of the bus, not the device. x86 > has such a mechanism, and this patch uses it transparently. Right. A device driver should use the DMA API. Always. The platform's implementation of the DMA API is then free to observe that the device in question isn't actually served by any IOMMU and give a trivial 1:1 mapping. > > > The virtio device should advertise whether it's using that bypass > > > mode of operation and virtio_pci should react accordingly. > > > > Well if there's a way to detect that - that's outside the > > device, then we probably shouldn't use device-specific > > interfaces for this capability. >=20 > (NB: According to David Woodhouse about ten minutes ago, this should > work with a bit of care right now on x86 via ACPI as long as QEMU > configures the tables correctly.) Well, we don't currently expose a virtual IOMMU to x86 guests at the moment although we're going to want to in the near future. My answer was based on the assumption that it'll actually be an Intel IOMMU that we expose, rather than some paravirtualised IOMMU interface which allows us to support both AMD and Intel hosts. That may not be a valid assumption; I don't think we've really explored this at all. But *given* that assumption, the VT-d ACPI tables allow a given IOMMU unit to be associated either with a list of specific devices, *or* to have a 'catch-all' bit set which means that it owns all otherwise-unmatched devices in that PCI domain. So... if you want some devices to be seen as *not* behind an IOMMU then they need to be in a PCI domain which *doesn't* have a catch-all IOMMU unit. So either you put them in a separate PCI domain all by themselves, or you explicitly list all (possible) PCI BDFs under the IOMMU unit and don't use the catch-all facility. =20 Having said that... don't. Just put the damn thing behind an IOMMU. The guest OS doesn't *have* to use it; it either eschew the IOMMU completely or it can choose to use pass-through mode for specific devices. --=20 David Woodhouse Open Source Technology Centre David.Woodhouse@intel.com Intel Corporation --=-6M6SbuO61NM4dJJLStt1 Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExCzAJBgUrDgMCGgUAMIAGCSqGSIb3DQEHAQAAoIISxDCCBjQw ggQcoAMCAQICAR4wDQYJKoZIhvcNAQEFBQAwfTELMAkGA1UEBhMCSUwxFjAUBgNVBAoTDVN0YXJ0 Q29tIEx0ZC4xKzApBgNVBAsTIlNlY3VyZSBEaWdpdGFsIENlcnRpZmljYXRlIFNpZ25pbmcxKTAn BgNVBAMTIFN0YXJ0Q29tIENlcnRpZmljYXRpb24gQXV0aG9yaXR5MB4XDTA3MTAyNDIxMDE1NVoX DTE3MTAyNDIxMDE1NVowgYwxCzAJBgNVBAYTAklMMRYwFAYDVQQKEw1TdGFydENvbSBMdGQuMSsw KQYDVQQLEyJTZWN1cmUgRGlnaXRhbCBDZXJ0aWZpY2F0ZSBTaWduaW5nMTgwNgYDVQQDEy9TdGFy dENvbSBDbGFzcyAxIFByaW1hcnkgSW50ZXJtZWRpYXRlIENsaWVudCBDQTCCASIwDQYJKoZIhvcN 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