From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:17588 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728042AbgBTMBP (ORCPT ); Thu, 20 Feb 2020 07:01:15 -0500 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01KC1AmM014621 for ; Thu, 20 Feb 2020 07:01:14 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2y8ucn0t0k-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 20 Feb 2020 07:01:11 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 20 Feb 2020 12:00:48 -0000 From: Pierre Morel Subject: [kvm-unit-tests PATCH v5 01/10] s390x: saving regs for interrupts Date: Thu, 20 Feb 2020 13:00:34 +0100 In-Reply-To: <1582200043-21760-1-git-send-email-pmorel@linux.ibm.com> References: <1582200043-21760-1-git-send-email-pmorel@linux.ibm.com> Message-Id: <1582200043-21760-2-git-send-email-pmorel@linux.ibm.com> Sender: linux-s390-owner@vger.kernel.org List-ID: To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com If we use multiple source of interrupts, for example, using SCLP console to print information while using I/O interrupts, we need to have a re-entrant register saving interruption handling. Instead of saving at a static memory address, let's save the base registers and the floating point registers on the stack. Note that we keep the static register saving to recover from the RESET tests. Signed-off-by: Pierre Morel --- s390x/cstart64.S | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 9af6bb3..45da523 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -118,6 +118,25 @@ memsetxc: lmg %r0, %r15, GEN_LC_SW_INT_GRS .endm +/* Save registers on the stack, so we can have stacked interrupts. */ + .macro SAVE_IRQ_REGS + slgfi %r15, 15 * 8 + stmg %r0, %r14, 0(%r15) + slgfi %r15, 16 * 8 + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + std \i, \i * 8(%r15) + .endr + .endm + + .macro RESTORE_IRQ_REGS + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ld \i, \i * 8(%r15) + .endr + algfi %r15, 16 * 8 + lmg %r0, %r14, 0(%r15) + algfi %r15, 15 * 8 + .endm + .section .text /* * load_reset calling convention: @@ -182,9 +201,9 @@ mcck_int: lpswe GEN_LC_MCCK_OLD_PSW io_int: - SAVE_REGS + SAVE_IRQ_REGS brasl %r14, handle_io_int - RESTORE_REGS + RESTORE_IRQ_REGS lpswe GEN_LC_IO_OLD_PSW svc_int: -- 2.17.0