From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:4982 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727964AbgBTMAx (ORCPT ); Thu, 20 Feb 2020 07:00:53 -0500 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01KBrrtv097273 for ; Thu, 20 Feb 2020 07:00:52 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2y99pfr5m7-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 20 Feb 2020 07:00:51 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 20 Feb 2020 12:00:49 -0000 From: Pierre Morel Subject: [kvm-unit-tests PATCH v5 03/10] s390x: cr0: adding AFP-register control bit Date: Thu, 20 Feb 2020 13:00:36 +0100 In-Reply-To: <1582200043-21760-1-git-send-email-pmorel@linux.ibm.com> References: <1582200043-21760-1-git-send-email-pmorel@linux.ibm.com> Message-Id: <1582200043-21760-4-git-send-email-pmorel@linux.ibm.com> Sender: linux-s390-owner@vger.kernel.org List-ID: To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com While adding the definition for the AFP-Register control bit, move all existing definitions for CR0 out of the C zone to the assmbler zone to keep the definitions concerning CR0 together. Signed-off-by: Pierre Morel --- lib/s390x/asm/arch_def.h | 11 ++++++----- s390x/cstart64.S | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index 69a8256..863c2bf 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -18,6 +18,12 @@ #define PSW_EXCEPTION_MASK (PSW_MASK_EA|PSW_MASK_BA) +#define CR0_EXTM_SCLP 0X0000000000000200UL +#define CR0_EXTM_EXTC 0X0000000000002000UL +#define CR0_EXTM_EMGC 0X0000000000004000UL +#define CR0_EXTM_MASK 0X0000000000006200UL +#define CR0_AFP_REG_CRTL 0x0000000000040000UL + #ifndef __ASSEMBLER__ struct psw { @@ -25,11 +31,6 @@ struct psw { uint64_t addr; }; -#define CR0_EXTM_SCLP 0X0000000000000200UL -#define CR0_EXTM_EXTC 0X0000000000002000UL -#define CR0_EXTM_EMGC 0X0000000000004000UL -#define CR0_EXTM_MASK 0X0000000000006200UL - struct lowcore { uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ uint32_t ext_int_param; /* 0x0080 */ diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 2885a36..3b59bd1 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -230,4 +230,4 @@ svc_int_psw: .quad PSW_EXCEPTION_MASK, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ - .quad 0x0000000000040000 + .quad CR0_AFP_REG_CRTL -- 2.17.0