From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:41000 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726883AbgDXKqC (ORCPT ); Fri, 24 Apr 2020 06:46:02 -0400 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAWb46124845 for ; Fri, 24 Apr 2020 06:46:02 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 30gmv32c6c-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 24 Apr 2020 06:46:02 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 24 Apr 2020 11:45:09 +0100 From: Pierre Morel Subject: [kvm-unit-tests PATCH v6 02/10] s390x: Use PSW bits definitions in cstart Date: Fri, 24 Apr 2020 12:45:44 +0200 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> Message-Id: <1587725152-25569-3-git-send-email-pmorel@linux.ibm.com> Sender: linux-s390-owner@vger.kernel.org List-ID: To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com This patch defines the PSW bits EA/BA used to initialize the PSW masks for exceptions. Since some PSW mask definitions exist already in arch_def.h we add these definitions there. We move all PSW definitions together and protect assembler code against C syntax. Signed-off-by: Pierre Morel --- lib/s390x/asm/arch_def.h | 16 ++++++++++++---- s390x/cstart64.S | 15 ++++++++------- 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index 15a4d49..c54409a 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -10,15 +10,22 @@ #ifndef _ASM_S390X_ARCH_DEF_H_ #define _ASM_S390X_ARCH_DEF_H_ +#define PSW_MASK_EXT 0x0100000000000000UL +#define PSW_MASK_DAT 0x0400000000000000UL +#define PSW_MASK_SHORT_PSW 0x0008000000000000UL +#define PSW_MASK_PSTATE 0x0001000000000000UL +#define PSW_MASK_BA 0x0000000080000000UL +#define PSW_MASK_EA 0x0000000100000000UL + +#define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) +#define PSW_RESET_MASK (PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW) + +#ifndef __ASSEMBLER__ struct psw { uint64_t mask; uint64_t addr; }; -#define PSW_MASK_EXT 0x0100000000000000UL -#define PSW_MASK_DAT 0x0400000000000000UL -#define PSW_MASK_PSTATE 0x0001000000000000UL - #define CR0_EXTM_SCLP 0X0000000000000200UL #define CR0_EXTM_EXTC 0X0000000000002000UL #define CR0_EXTM_EMGC 0X0000000000004000UL @@ -297,4 +304,5 @@ static inline uint32_t get_prefix(void) return current_prefix; } +#endif /* __ASSEMBLER */ #endif diff --git a/s390x/cstart64.S b/s390x/cstart64.S index ba2e67c..e394b3a 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -12,6 +12,7 @@ */ #include #include +#include .section .init @@ -225,19 +226,19 @@ svc_int: .align 8 reset_psw: - .quad 0x0008000180000000 + .quad PSW_RESET_MASK initial_psw: - .quad 0x0000000180000000, clear_bss_start + .quad PSW_EXCEPTION_MASK, clear_bss_start pgm_int_psw: - .quad 0x0000000180000000, pgm_int + .quad PSW_EXCEPTION_MASK, pgm_int ext_int_psw: - .quad 0x0000000180000000, ext_int + .quad PSW_EXCEPTION_MASK, ext_int mcck_int_psw: - .quad 0x0000000180000000, mcck_int + .quad PSW_EXCEPTION_MASK, mcck_int io_int_psw: - .quad 0x0000000180000000, io_int + .quad PSW_EXCEPTION_MASK, io_int svc_int_psw: - .quad 0x0000000180000000, svc_int + .quad PSW_EXCEPTION_MASK, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ .quad 0x0000000000040000 -- 2.25.1