From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:26744 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726041AbgDVJGi (ORCPT ); Wed, 22 Apr 2020 05:06:38 -0400 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03M95E8K090875 for ; Wed, 22 Apr 2020 05:06:36 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0b-001b2d01.pphosted.com with ESMTP id 30gcs5ckww-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 22 Apr 2020 05:06:36 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 22 Apr 2020 10:06:29 +0100 Subject: Re: [kvm-unit-tests PATCH v5 02/10] s390x: Use PSW bits definitions in cstart References: <1582200043-21760-1-git-send-email-pmorel@linux.ibm.com> <1582200043-21760-3-git-send-email-pmorel@linux.ibm.com> From: Pierre Morel Date: Wed, 22 Apr 2020 11:06:31 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Message-Id: <1b38a0e5-76cf-c3da-fe8d-7a75bf44f19f@linux.ibm.com> Sender: linux-s390-owner@vger.kernel.org List-ID: To: Janosch Frank , kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, david@redhat.com, thuth@redhat.com, cohuck@redhat.com On 2020-04-22 09:35, Janosch Frank wrote: > On 2/20/20 1:00 PM, Pierre Morel wrote: >> This patch defines the PSW bits EA/BA used to initialize the PSW masks >> for exceptions. >> >> Since some PSW mask definitions exist already in arch_def.h we add these >> definitions there. >> We move all PSW definitions together and protect assembler code against >> C syntax. > > Please fix the issue mentioned below and run *all* tests against your > new code to verify you didn't introduce regressions. > > The rest looks good to me. Thanks, > >> >> Signed-off-by: Pierre Morel >> --- >> lib/s390x/asm/arch_def.h | 15 +++++++++++---- >> s390x/cstart64.S | 15 ++++++++------- >> 2 files changed, 19 insertions(+), 11 deletions(-) >> >> diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h >> index 15a4d49..69a8256 100644 >> --- a/lib/s390x/asm/arch_def.h >> +++ b/lib/s390x/asm/arch_def.h >> @@ -10,15 +10,21 @@ >> #ifndef _ASM_S390X_ARCH_DEF_H_ >> #define _ASM_S390X_ARCH_DEF_H_ >> >> +#define PSW_MASK_EXT 0x0100000000000000UL >> +#define PSW_MASK_DAT 0x0400000000000000UL >> +#define PSW_MASK_PSTATE 0x0001000000000000UL >> +#define PSW_MASK_BA 0x0000000080000000UL >> +#define PSW_MASK_EA 0x0000000100000000UL >> + >> +#define PSW_EXCEPTION_MASK (PSW_MASK_EA|PSW_MASK_BA) > > Could you add a space before and after the | ? > >> + >> +#ifndef __ASSEMBLER__ >> + >> struct psw { >> uint64_t mask; >> uint64_t addr; >> }; >> >> -#define PSW_MASK_EXT 0x0100000000000000UL >> -#define PSW_MASK_DAT 0x0400000000000000UL >> -#define PSW_MASK_PSTATE 0x0001000000000000UL >> - >> #define CR0_EXTM_SCLP 0X0000000000000200UL >> #define CR0_EXTM_EXTC 0X0000000000002000UL >> #define CR0_EXTM_EMGC 0X0000000000004000UL >> @@ -297,4 +303,5 @@ static inline uint32_t get_prefix(void) >> return current_prefix; >> } >> >> +#endif /* not __ASSEMBLER__ */ >> #endif >> diff --git a/s390x/cstart64.S b/s390x/cstart64.S >> index 45da523..2885a36 100644 >> --- a/s390x/cstart64.S >> +++ b/s390x/cstart64.S >> @@ -12,6 +12,7 @@ >> */ >> #include >> #include >> +#include >> >> .section .init >> >> @@ -214,19 +215,19 @@ svc_int: >> >> .align 8 >> reset_psw: >> - .quad 0x0008000180000000 >> + .quad PSW_EXCEPTION_MASK > > That won't work, this is a short PSW and you're removing the short > indication here. Notice the 0008 at the front. > Will change and define PSW_MASK_SHORT_PSW and PSW_RESET_MASK like: #define PSW_MASK_SHORT_PSW 0x0008000000000000UL ... #define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA) #define PSW_RESET_MASK (PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW) -- Pierre Morel IBM Lab Boeblingen