[kvm-unit-tests PATCH v3 0/8] s390x: Extend instruction interception tests

[kvm-unit-tests PATCH v3 0/8] s390x: Extend instruction interception tests

[Nico Boehr]

This series extends the instruction interception tests for s390x.

For most instructions, there is already coverage in existing tests, but they are
not covering some failure cases, e.g. bad alignment. In this case, the existing
tests were extended.

SCK was not under test anywhere yet, hence a new test file was added.

The EPSW test gets it's own file, too, because it requires a I/O device, more
details in the respective commit. 

Changelog from v2:
----
- Don't run the sck test under PV
- Include commit of the QEMU PMCW fix in the MSCH and STSCH commit messages

Nico Boehr (8):
  s390x: Add more tests for MSCH
  s390x: Add test for PFMF low-address protection
  s390x: Add sck tests
  s390x: Add tests for STCRW
  s390x: Add more tests for SSCH
  s390x: Add more tests for STSCH
  s390x: Add tests for TSCH
  s390x: Add EPSW test

 lib/s390x/css.h     |  17 +++
 lib/s390x/css_lib.c |  60 ++++++++++
 s390x/Makefile      |   2 +
 s390x/css.c         | 278 ++++++++++++++++++++++++++++++++++++++++++++
 s390x/epsw.c        | 113 ++++++++++++++++++
 s390x/pfmf.c        |  29 +++++
 s390x/sck.c         | 134 +++++++++++++++++++++
 s390x/unittests.cfg |   7 ++
 8 files changed, 640 insertions(+)
 create mode 100644 s390x/epsw.c
 create mode 100644 s390x/sck.c

-- 
2.31.1

[kvm-unit-tests PATCH v3 1/8] s390x: Add more tests for MSCH

[Nico Boehr]

We already have some coverage for MSCH, but there are more cases to test
for:

- invalid SCHIB structure. We cover that by setting reserved bits 0, 1,
  6 and 7 in the flags of the PMCW.
  Older QEMU versions require this bit to always be zero on msch,
  which is why this test may fail. A fix is available in QEMU master
  commit 2df59b73e086 ("s390x/css: fix PMCW invalid mask").
- a pointer to an unaligned SCHIB. We cover misalignment by 1
  and 2 bytes. Using pointer to valid memory avoids messing up
  random memory in case of test failures.

Here's the QEMU PMCW invalid mask fix: https://lists.nongnu.org/archive/html/qemu-s390x/2021-12/msg00100.html

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
 s390x/css.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/s390x/css.c b/s390x/css.c
index 881206ba1cef..932daf69bb36 100644
--- a/s390x/css.c
+++ b/s390x/css.c
@@ -27,6 +27,8 @@ static int test_device_sid;
 static struct senseid *senseid;
 struct ccw1 *ccw;
 
+char alignment_test_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
+
 static void test_enumerate(void)
 {
 	test_device_sid = css_enumerate();
@@ -331,6 +333,56 @@ static void test_schm_fmt1(void)
 	free_io_mem(mb1, sizeof(struct measurement_block_format1));
 }
 
+static void test_msch(void)
+{
+	const int align_to = 4;
+	int cc;
+	int invalid_pmcw_flags[] = {0, 1, 6, 7};
+	int invalid_flag;
+	uint16_t old_pmcw_flags;
+
+	if (!test_device_sid) {
+		report_skip("No device");
+		return;
+	}
+
+	cc = stsch(test_device_sid, &schib);
+	if (cc) {
+		report_fail("stsch: sch %08x failed with cc=%d", test_device_sid, cc);
+		return;
+	}
+
+	report_prefix_push("Unaligned");
+	for (int i = 1; i < align_to; i *= 2) {
+		report_prefix_pushf("%d", i);
+
+		expect_pgm_int();
+		msch(test_device_sid, (struct schib *)(alignment_test_page + i));
+		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+
+	report_prefix_push("Invalid SCHIB");
+	old_pmcw_flags = schib.pmcw.flags;
+	for (int i = 0; i < ARRAY_SIZE(invalid_pmcw_flags); i++) {
+		invalid_flag = invalid_pmcw_flags[i];
+
+		report_prefix_pushf("PMCW flag bit %d set", invalid_flag);
+
+		schib.pmcw.flags = old_pmcw_flags | BIT(15 - invalid_flag);
+		expect_pgm_int();
+		msch(test_device_sid, &schib);
+		check_pgm_int_code(PGM_INT_CODE_OPERAND);
+
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+
+	schib.pmcw.flags = old_pmcw_flags;
+}
+
 static struct {
 	const char *name;
 	void (*func)(void);
@@ -343,6 +395,7 @@ static struct {
 	{ "measurement block (schm)", test_schm },
 	{ "measurement block format0", test_schm_fmt0 },
 	{ "measurement block format1", test_schm_fmt1 },
+	{ "msch", test_msch },
 	{ NULL, NULL }
 };
 
-- 
2.31.1

[kvm-unit-tests PATCH v3 2/8] s390x: Add test for PFMF low-address protection

[Nico Boehr]

PFMF should respect the low-address protection when clearing pages, hence
add some tests for it.

When low-address protection fails, clearing frame 0 is a destructive
operation. It messes up interrupts and thus printing test results won't
work properly. Hence, we first attempt to clear frame 1 which is not as
destructive.

Doing it this way around increases the chances for the user to see a
proper failure message instead of QEMU randomly quitting in the middle
of the test run.

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
 s390x/pfmf.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/s390x/pfmf.c b/s390x/pfmf.c
index 2f3cb110dc4c..aa1305292ee8 100644
--- a/s390x/pfmf.c
+++ b/s390x/pfmf.c
@@ -113,6 +113,34 @@ static void test_1m_clear(void)
 	report_prefix_pop();
 }
 
+static void test_low_addr_prot(void)
+{
+	union pfmf_r1 r1 = {
+		.reg.cf = 1,
+		.reg.fsc = PFMF_FSC_4K
+	};
+
+	report_prefix_push("low-address protection");
+
+	report_prefix_push("0x1000");
+	expect_pgm_int();
+	low_prot_enable();
+	pfmf(r1.val, (void *)0x1000);
+	low_prot_disable();
+	check_pgm_int_code(PGM_INT_CODE_PROTECTION);
+	report_prefix_pop();
+
+	report_prefix_push("0x0");
+	expect_pgm_int();
+	low_prot_enable();
+	pfmf(r1.val, 0);
+	low_prot_disable();
+	check_pgm_int_code(PGM_INT_CODE_PROTECTION);
+	report_prefix_pop();
+
+	report_prefix_pop();
+}
+
 int main(void)
 {
 	bool has_edat = test_facility(8);
@@ -124,6 +152,7 @@ int main(void)
 	}
 
 	test_priv();
+	test_low_addr_prot();
 	/* Force the buffer pages in */
 	memset(pagebuf, 0, PAGE_SIZE * 256);
 
-- 
2.31.1

[kvm-unit-tests PATCH v3 3/8] s390x: Add sck tests

[Nico Boehr]

SCK updates the guest's TOD clock. It needs to be intercepted, hence we
should have some tests for it:

- its operand must be 8-byte aligned. We test for 1, 2 and 4 byte
  misalignment.
- it should actually update the clock value. As guests are unable to
  stop their clock, we can only check the clock value is at least higher
  than the value we set.
- it is a privileged call, so expect it to fail when in problem state.
  We also test the clock value is not changed in this case. We do so by first
  adjusting it (privileged) to a high value. We then attempt, in
  nonprivileged mode, to set the clock to a comparatively small value.
  We can then store the clock value and test its value is strictly higher
  than the high value we set previously.

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.ibm.com>
---
 s390x/Makefile      |   1 +
 s390x/sck.c         | 134 ++++++++++++++++++++++++++++++++++++++++++++
 s390x/unittests.cfg |   3 +
 3 files changed, 138 insertions(+)
 create mode 100644 s390x/sck.c

diff --git a/s390x/Makefile b/s390x/Makefile
index 53b0fe044fe7..a76b78e5a011 100644
--- a/s390x/Makefile
+++ b/s390x/Makefile
@@ -17,6 +17,7 @@ tests += $(TEST_DIR)/stsi.elf
 tests += $(TEST_DIR)/skrf.elf
 tests += $(TEST_DIR)/smp.elf
 tests += $(TEST_DIR)/sclp.elf
+tests += $(TEST_DIR)/sck.elf
 tests += $(TEST_DIR)/css.elf
 tests += $(TEST_DIR)/uv-guest.elf
 tests += $(TEST_DIR)/sie.elf
diff --git a/s390x/sck.c b/s390x/sck.c
new file mode 100644
index 000000000000..49a9e28dafc8
--- /dev/null
+++ b/s390x/sck.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Perform Set Clock tests
+ *
+ * Copyright IBM Corp. 2022
+ *
+ * Authors:
+ *  Nico Boehr <nrb@linux.ibm.com>
+ */
+#include <libcflat.h>
+#include <uv.h>
+#include <asm/interrupt.h>
+#include <asm/time.h>
+
+static inline int sck(uint64_t *time)
+{
+	int cc;
+
+	asm volatile(
+		"	sck %[time]\n"
+		"	ipm %[cc]\n"
+		"	srl %[cc],28\n"
+		: [cc] "=d"(cc)
+		: [time] "Q"(*time)
+		: "cc"
+	);
+
+	return cc;
+}
+
+static inline int stck(uint64_t *time)
+{
+	int cc;
+
+	asm volatile(
+		"	stck %[time]\n"
+		"	ipm %[cc]\n"
+		"	srl %[cc],28\n"
+		: [cc] "=d" (cc), [time] "=Q" (*time)
+		:
+		: "cc", "memory"
+	);
+
+	return cc;
+}
+
+static void test_priv(void)
+{
+	uint64_t time_to_set_privileged = 0xfacef00dcafe0000,
+	    time_to_set_nonprivileged = 0xcafe0000,
+	    time_verify;
+	int cc;
+
+	report_prefix_push("privileged");
+	cc = sck(&time_to_set_privileged);
+	report(!cc, "set clock cc=%d", cc);
+
+	cc = stck(&time_verify);
+	report(!cc, "store clock cc=%d", cc);
+	report(time_verify > time_to_set_privileged,
+	       "privileged set affected the clock");
+
+	expect_pgm_int();
+	enter_pstate();
+	sck(&time_to_set_nonprivileged);
+	leave_pstate();
+	check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION);
+
+	cc = stck(&time_verify);
+	report(!cc, "store clock cc=%d", cc);
+	report(time_verify > time_to_set_privileged,
+	       "unprivileged set did not affect the clock");
+	report_prefix_pop();
+}
+
+static void test_align(void)
+{
+	const int align_to = 8;
+	char unalign[sizeof(uint64_t) + align_to] __attribute__((aligned(8)));
+
+	report_prefix_push("Unaligned operand");
+	for (int i = 1; i < align_to; i *= 2) {
+		report_prefix_pushf("%d", i);
+		expect_pgm_int();
+		sck((uint64_t *)(unalign + i));
+		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+}
+
+static void test_set(void)
+{
+	uint64_t start = 0, end = 0, time = 0xcafef00dbeef;
+	const uint64_t ticks_per_ms = 1000 << 12, ms_to_wait = 5;
+	int cc;
+
+	report_prefix_push("set");
+
+	cc = sck(&time);
+	report(!cc, "set clock cc=%d", cc);
+
+	cc = stck(&start);
+	report(!cc, "store start clock cc=%d", cc);
+	report(start >= time, "start >= set value");
+
+	mdelay(ms_to_wait);
+
+	cc = stck(&end);
+	report(!cc, "store end clock cc=%d", cc);
+	report(end > time, "end > set value");
+
+	report(end - start > (ticks_per_ms * ms_to_wait), "Advances");
+
+	report_prefix_pop();
+}
+
+int main(void)
+{
+	report_prefix_push("sck");
+
+	if (uv_os_is_guest()) {
+		report_skip("Test unsupported under PV");
+		goto out;
+	}
+
+	test_align();
+	test_set();
+	test_priv();
+
+out:
+	report_prefix_pop();
+	return report_summary();
+}
diff --git a/s390x/unittests.cfg b/s390x/unittests.cfg
index 1600e714c8b9..8b148fe31ac0 100644
--- a/s390x/unittests.cfg
+++ b/s390x/unittests.cfg
@@ -136,3 +136,6 @@ file = firq.elf
 timeout = 20
 extra_params = -smp 1,maxcpus=3 -cpu qemu -device qemu-s390x-cpu,core-id=2 -device qemu-s390x-cpu,core-id=1
 accel = tcg
+
+[sck]
+file = sck.elf
-- 
2.31.1

[kvm-unit-tests PATCH v3 4/8] s390x: Add tests for STCRW

[Nico Boehr]

The test consists of two parts: First a simple check to ensure we
enforce an aligned address. We test misalignment by 1 and 2 bytes.

The second part tests the handling of pending Channel Reports (CR). We
first assume no CR is initally pending and check STCRW returns
accordingly. Then, we generate a CR by resetting a Channel Path using
RCHP and make sure this results in exactly one CRW being generated which
has a Reporting-Source Code (RSC) corresponding to the Channel Path
facility.

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.ibm.com>
---
 lib/s390x/css.h     | 17 ++++++++++
 lib/s390x/css_lib.c | 60 +++++++++++++++++++++++++++++++++
 s390x/css.c         | 82 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 159 insertions(+)

diff --git a/lib/s390x/css.h b/lib/s390x/css.h
index 0db8a28166f6..a6a68577248b 100644
--- a/lib/s390x/css.h
+++ b/lib/s390x/css.h
@@ -266,6 +266,20 @@ static inline int rchp(unsigned long chpid)
 	return cc;
 }
 
+static inline int stcrw(uint32_t *crw)
+{
+	int cc;
+
+	asm volatile(
+		"	stcrw	%[crw]\n"
+		"	ipm	%[cc]\n"
+		"	srl	%[cc],28"
+		: [cc] "=d" (cc)
+		: [crw] "Q" (*crw)
+		: "cc", "memory");
+	return cc;
+}
+
 /* Debug functions */
 char *dump_pmcw_flags(uint16_t f);
 char *dump_scsw_flags(uint32_t f);
@@ -294,6 +308,9 @@ int css_residual_count(unsigned int schid);
 void enable_io_isc(uint8_t isc);
 int wait_and_check_io_completion(int schid);
 
+int css_find_installed_chpid(int sid, uint8_t *chpid_out);
+int css_generate_crw(int sid);
+
 /*
  * CHSC definitions
  */
diff --git a/lib/s390x/css_lib.c b/lib/s390x/css_lib.c
index 80e9e078b0f6..a9f5097f3486 100644
--- a/lib/s390x/css_lib.c
+++ b/lib/s390x/css_lib.c
@@ -504,3 +504,63 @@ void enable_io_isc(uint8_t isc)
 	value = (uint64_t)isc << 24;
 	lctlg(6, value);
 }
+
+static int is_path_installed(struct schib *schib, int chp_idx)
+{
+	return schib->pmcw.pim & BIT(7 - chp_idx);
+}
+
+/*
+ * css_find_installed_chpid: find any installed CHPID
+ * @sid: subsystem-identification word
+ * @chpid_out: store the found chpid here, left alone if none found
+ *
+ * returns 0 on success, -1 if no chpid found any other value
+ * indicates the condition code of a failing STSCH instruction
+ */
+int css_find_installed_chpid(int sid, uint8_t *chpid_out)
+{
+	int cc;
+
+	cc = stsch(sid, &schib);
+	if (cc) {
+		report_fail("%s: sch %08x failed with cc=%d", __func__, sid, cc);
+		return cc;
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(schib.pmcw.chpid); i++) {
+		if (is_path_installed(&schib, i)) {
+			*chpid_out = schib.pmcw.chpid[i];
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+/*
+ * css_generate_crw: Generate a CRW by issuing RCHP on any channel path
+ * @sid: subsystem-identification word
+ *
+ * returns 0 when a CRW was generated, -1 if no chpid found.
+ */
+int css_generate_crw(int sid)
+{
+	int ret, cc;
+	uint8_t chpid;
+
+	report_prefix_push("Generate CRW");
+
+	ret = css_find_installed_chpid(sid, &chpid);
+	if (ret) {
+		report_fail("No CHPID found: ret=%d", ret);
+		return -1;
+	}
+
+	cc = rchp(chpid);
+	report(!cc, "rhcp cc != 0");
+
+	report_prefix_pop();
+
+	return 0;
+}
diff --git a/s390x/css.c b/s390x/css.c
index 932daf69bb36..6a2db79c8097 100644
--- a/s390x/css.c
+++ b/s390x/css.c
@@ -383,6 +383,87 @@ static void test_msch(void)
 	schib.pmcw.flags = old_pmcw_flags;
 }
 
+static void check_stcrw_no_crw_available(void)
+{
+	uint32_t crw = 0xfeedc0fe;
+	int cc;
+
+	report_prefix_push("No CRW available");
+	cc = stcrw(&crw);
+	report(cc == 1, "cc == 1");
+	report(!crw, "stored zeroes in crw");
+	report_prefix_pop();
+}
+
+static int check_stcrw_crw_available(void)
+{
+	const uint32_t magic = 0xfeedc0fe;
+	uint32_t crw = magic;
+	int cc;
+
+	report_prefix_push("CRW available");
+	cc = stcrw(&crw);
+	report(!cc, "cc is zero");
+	report(crw != magic, "stored crw");
+	report_prefix_pop();
+
+	return crw;
+}
+
+static uint32_t crw_get_rsc(uint32_t crw)
+{
+	const int rsc_begin = 4;
+	const int rsc_end = 8;
+
+	return (crw & GENMASK(31 - rsc_begin, 31 - rsc_end)) >> 24;
+}
+
+#define CRW_RSC_CHP 4
+static void test_stcrw(void)
+{
+	const int align_to = 4;
+	int res;
+	uint32_t crw;
+
+	if (!test_device_sid) {
+		report_skip("No device");
+		return;
+	}
+
+	report_prefix_push("Unaligned");
+	for (int i = 1; i < align_to; i *= 2) {
+		report_prefix_pushf("%d", i);
+
+		expect_pgm_int();
+		stcrw((uint32_t *)(alignment_test_page + i));
+		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+
+	report_prefix_push("No CRW available initally");
+	check_stcrw_no_crw_available();
+	report_prefix_pop();
+
+	res = css_generate_crw(test_device_sid);
+	if (res) {
+		report_skip("Couldn't generate CRW");
+		report_prefix_pop();
+		return;
+	}
+
+	crw = check_stcrw_crw_available();
+
+	report_prefix_push("CRW available");
+	report(crw_get_rsc(crw) == CRW_RSC_CHP, "CRW has Channel Path RSC");
+	report_prefix_pop();
+
+	report_prefix_push("No more CRWs pending");
+	check_stcrw_no_crw_available();
+	report_prefix_pop();
+}
+
 static struct {
 	const char *name;
 	void (*func)(void);
@@ -396,6 +477,7 @@ static struct {
 	{ "measurement block format0", test_schm_fmt0 },
 	{ "measurement block format1", test_schm_fmt1 },
 	{ "msch", test_msch },
+	{ "stcrw", test_stcrw },
 	{ NULL, NULL }
 };
 
-- 
2.31.1

[kvm-unit-tests PATCH v3 5/8] s390x: Add more tests for SSCH

[Nico Boehr]

We already have some coverage of SSCH due to its use in
start_ccw1_chain() in css_lib, but two more cases deserve our
attention:

- unaligned operand address. We check for misalignment by 1 and 2 bytes.
- an invalid ORB structure.

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.ibm.com>
---
 s390x/css.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/s390x/css.c b/s390x/css.c
index 6a2db79c8097..a90a0cd64e2b 100644
--- a/s390x/css.c
+++ b/s390x/css.c
@@ -464,6 +464,38 @@ static void test_stcrw(void)
 	report_prefix_pop();
 }
 
+static void test_ssch(void)
+{
+	const int align_to = 4;
+	struct orb orb;
+
+	if (!test_device_sid) {
+		report_skip("No device");
+		return;
+	}
+
+	report_prefix_push("Unaligned");
+	for (int i = 1; i < align_to; i *= 2) {
+		report_prefix_pushf("%d", i);
+
+		expect_pgm_int();
+		ssch(test_device_sid, (struct orb *)(alignment_test_page + i));
+		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+
+	report_prefix_push("Invalid ORB");
+
+	memset(&orb, 0xff, sizeof(orb));
+	expect_pgm_int();
+	ssch(test_device_sid, &orb);
+	check_pgm_int_code(PGM_INT_CODE_OPERAND);
+
+	report_prefix_pop();
+}
+
 static struct {
 	const char *name;
 	void (*func)(void);
@@ -478,6 +510,7 @@ static struct {
 	{ "measurement block format1", test_schm_fmt1 },
 	{ "msch", test_msch },
 	{ "stcrw", test_stcrw },
+	{ "ssch", test_ssch },
 	{ NULL, NULL }
 };
 
-- 
2.31.1

[kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Nico Boehr]

css_lib extensively uses STSCH, but two more cases deserve their own
tests:

- unaligned address for SCHIB. We check for misalignment by 1 and 2
  bytes.
- channel not operational
- bit 47 in SID not set
- bit 5 of PMCW flags.
  As per the principles of operation, bit 5 of the PMCW flags shall be
  ignored by msch and always stored as zero by stsch.

  Older QEMU versions require this bit to always be zero on msch,
  which is why this test may fail. A fix is available in QEMU master
  commit 2df59b73e086 ("s390x/css: fix PMCW invalid mask").

Here's the QEMU PMCW invalid mask fix: https://lists.nongnu.org/archive/html/qemu-s390x/2021-12/msg00100.html

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
---
 s390x/css.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/s390x/css.c b/s390x/css.c
index a90a0cd64e2b..021eb12573c0 100644
--- a/s390x/css.c
+++ b/s390x/css.c
@@ -496,6 +496,78 @@ static void test_ssch(void)
 	report_prefix_pop();
 }
 
+static void test_stsch(void)
+{
+	const int align_to = 4;
+	struct schib schib;
+	int cc;
+
+	if (!test_device_sid) {
+		report_skip("No device");
+		return;
+	}
+
+	report_prefix_push("Unaligned");
+	for (int i = 1; i < align_to; i *= 2) {
+		report_prefix_pushf("%d", i);
+
+		expect_pgm_int();
+		stsch(test_device_sid, (struct schib *)(alignment_test_page + i));
+		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+
+	report_prefix_push("Invalid subchannel number");
+	cc = stsch(0x0001ffff, &schib);
+	report(cc == 3, "Channel not operational");
+	report_prefix_pop();
+
+	report_prefix_push("Bit 47 in SID is zero");
+	expect_pgm_int();
+	stsch(0x0000ffff, &schib);
+	check_pgm_int_code(PGM_INT_CODE_OPERAND);
+	report_prefix_pop();
+}
+
+static void test_pmcw_bit5(void)
+{
+	int cc;
+	uint16_t old_pmcw_flags;
+
+	cc = stsch(test_device_sid, &schib);
+	if (cc) {
+		report_fail("stsch: sch %08x failed with cc=%d", test_device_sid, cc);
+		return;
+	}
+	old_pmcw_flags = schib.pmcw.flags;
+
+	report_prefix_push("Bit 5 set");
+
+	schib.pmcw.flags = old_pmcw_flags | BIT(15 - 5);
+	cc = msch(test_device_sid, &schib);
+	report(!cc, "MSCH cc == 0");
+
+	cc = stsch(test_device_sid, &schib);
+	report(!cc, "STSCH cc == 0");
+	report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is clear");
+
+	report_prefix_pop();
+
+	report_prefix_push("Bit 5 clear");
+
+	schib.pmcw.flags = old_pmcw_flags & ~BIT(15 - 5);
+	cc = msch(test_device_sid, &schib);
+	report(!cc, "MSCH cc == 0");
+
+	cc = stsch(test_device_sid, &schib);
+	report(!cc, "STSCH cc == 0");
+	report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is clear");
+
+	report_prefix_pop();
+}
+
 static struct {
 	const char *name;
 	void (*func)(void);
@@ -511,6 +583,8 @@ static struct {
 	{ "msch", test_msch },
 	{ "stcrw", test_stcrw },
 	{ "ssch", test_ssch },
+	{ "stsch", test_stsch },
+	{ "pmcw bit 5 ignored", test_pmcw_bit5 },
 	{ NULL, NULL }
 };
 
-- 
2.31.1

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Claudio Imbrenda]

On Wed, 23 Feb 2022 14:29:38 +0100
Nico Boehr <nrb@linux.ibm.com> wrote:

> css_lib extensively uses STSCH, but two more cases deserve their own
> tests:
> 
> - unaligned address for SCHIB. We check for misalignment by 1 and 2
>   bytes.
> - channel not operational
> - bit 47 in SID not set
> - bit 5 of PMCW flags.
>   As per the principles of operation, bit 5 of the PMCW flags shall be
>   ignored by msch and always stored as zero by stsch.
> 
>   Older QEMU versions require this bit to always be zero on msch,
>   which is why this test may fail. A fix is available in QEMU master
>   commit 2df59b73e086 ("s390x/css: fix PMCW invalid mask").
> 
> Here's the QEMU PMCW invalid mask fix: https://lists.nongnu.org/archive/html/qemu-s390x/2021-12/msg00100.html
> 
> Signed-off-by: Nico Boehr <nrb@linux.ibm.com>

Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>

> ---
>  s390x/css.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/s390x/css.c b/s390x/css.c
> index a90a0cd64e2b..021eb12573c0 100644
> --- a/s390x/css.c
> +++ b/s390x/css.c
> @@ -496,6 +496,78 @@ static void test_ssch(void)
>  	report_prefix_pop();
>  }
>  
> +static void test_stsch(void)
> +{
> +	const int align_to = 4;
> +	struct schib schib;
> +	int cc;
> +
> +	if (!test_device_sid) {
> +		report_skip("No device");
> +		return;
> +	}
> +
> +	report_prefix_push("Unaligned");
> +	for (int i = 1; i < align_to; i *= 2) {
> +		report_prefix_pushf("%d", i);
> +
> +		expect_pgm_int();
> +		stsch(test_device_sid, (struct schib *)(alignment_test_page + i));
> +		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
> +
> +		report_prefix_pop();
> +	}
> +	report_prefix_pop();
> +
> +	report_prefix_push("Invalid subchannel number");
> +	cc = stsch(0x0001ffff, &schib);
> +	report(cc == 3, "Channel not operational");
> +	report_prefix_pop();
> +
> +	report_prefix_push("Bit 47 in SID is zero");
> +	expect_pgm_int();
> +	stsch(0x0000ffff, &schib);
> +	check_pgm_int_code(PGM_INT_CODE_OPERAND);
> +	report_prefix_pop();
> +}
> +
> +static void test_pmcw_bit5(void)
> +{
> +	int cc;
> +	uint16_t old_pmcw_flags;
> +
> +	cc = stsch(test_device_sid, &schib);
> +	if (cc) {
> +		report_fail("stsch: sch %08x failed with cc=%d", test_device_sid, cc);
> +		return;
> +	}
> +	old_pmcw_flags = schib.pmcw.flags;
> +
> +	report_prefix_push("Bit 5 set");
> +
> +	schib.pmcw.flags = old_pmcw_flags | BIT(15 - 5);
> +	cc = msch(test_device_sid, &schib);
> +	report(!cc, "MSCH cc == 0");
> +
> +	cc = stsch(test_device_sid, &schib);
> +	report(!cc, "STSCH cc == 0");
> +	report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is clear");
> +
> +	report_prefix_pop();
> +
> +	report_prefix_push("Bit 5 clear");
> +
> +	schib.pmcw.flags = old_pmcw_flags & ~BIT(15 - 5);
> +	cc = msch(test_device_sid, &schib);
> +	report(!cc, "MSCH cc == 0");
> +
> +	cc = stsch(test_device_sid, &schib);
> +	report(!cc, "STSCH cc == 0");
> +	report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is clear");
> +
> +	report_prefix_pop();
> +}
> +
>  static struct {
>  	const char *name;
>  	void (*func)(void);
> @@ -511,6 +583,8 @@ static struct {
>  	{ "msch", test_msch },
>  	{ "stcrw", test_stcrw },
>  	{ "ssch", test_ssch },
> +	{ "stsch", test_stsch },
> +	{ "pmcw bit 5 ignored", test_pmcw_bit5 },
>  	{ NULL, NULL }
>  };
>  

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Janosch Frank]

On 2/23/22 14:29, Nico Boehr wrote:
> css_lib extensively uses STSCH, but two more cases deserve their own
> tests:
> 
> - unaligned address for SCHIB. We check for misalignment by 1 and 2
>    bytes.
> - channel not operational
> - bit 47 in SID not set
> - bit 5 of PMCW flags.
>    As per the principles of operation, bit 5 of the PMCW flags shall be
>    ignored by msch and always stored as zero by stsch.
> 
>    Older QEMU versions require this bit to always be zero on msch,
>    which is why this test may fail. A fix is available in QEMU master
>    commit 2df59b73e086 ("s390x/css: fix PMCW invalid mask"). >
> Here's the QEMU PMCW invalid mask fix: https://lists.nongnu.org/archive/html/qemu-s390x/2021-12/msg00100.html
> 
> Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
> ---
>   s390x/css.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 74 insertions(+)
> 
> diff --git a/s390x/css.c b/s390x/css.c
> index a90a0cd64e2b..021eb12573c0 100644
> --- a/s390x/css.c
> +++ b/s390x/css.c
> @@ -496,6 +496,78 @@ static void test_ssch(void)
>   	report_prefix_pop();
>   }
>   
> +static void test_stsch(void)
> +{
> +	const int align_to = 4;
> +	struct schib schib;
> +	int cc;
> +
> +	if (!test_device_sid) {
> +		report_skip("No device");
> +		return;
> +	}
> +
> +	report_prefix_push("Unaligned");
> +	for (int i = 1; i < align_to; i *= 2) {
> +		report_prefix_pushf("%d", i);
> +
> +		expect_pgm_int();
> +		stsch(test_device_sid, (struct schib *)(alignment_test_page + i));
> +		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
> +
> +		report_prefix_pop();
> +	}
> +	report_prefix_pop();
> +
> +	report_prefix_push("Invalid subchannel number");
> +	cc = stsch(0x0001ffff, &schib);
> +	report(cc == 3, "Channel not operational");
> +	report_prefix_pop();
> +
> +	report_prefix_push("Bit 47 in SID is zero");
> +	expect_pgm_int();
> +	stsch(0x0000ffff, &schib);
> +	check_pgm_int_code(PGM_INT_CODE_OPERAND);
> +	report_prefix_pop();

Add a comment:
No matter if the multiple-subchannel-set facility is installed or not, 
bit 47 always needs to be 1.

Do we have the MSS facility?
If yes, could we disable it to test the 32-47 == 0x0001 case?

> +}
> +
> +static void test_pmcw_bit5(void)
> +{
> +	int cc;
> +	uint16_t old_pmcw_flags;

I need a comment here for further reference since that behavior is 
documented at the description of the schib and not where STSCH is described:
According to architecture MSCH does ignore bit 5 of the second word but 
STSCH will store bit 5 as zero.


We could check if bits 0,1 and 6,7 are also zero but I'm not sure if 
that's interesting since MSCH does not ignore those bits and should 
result in an operand exception when trying to set them.

@Halil, @Pierre: Any opinions?

> +
> +	cc = stsch(test_device_sid, &schib);
> +	if (cc) {
> +		report_fail("stsch: sch %08x failed with cc=%d", test_device_sid, cc);
> +		return;
> +	}
> +	old_pmcw_flags = schib.pmcw.flags;
> +
> +	report_prefix_push("Bit 5 set");
> +
> +	schib.pmcw.flags = old_pmcw_flags | BIT(15 - 5);
> +	cc = msch(test_device_sid, &schib);
> +	report(!cc, "MSCH cc == 0");
> +
> +	cc = stsch(test_device_sid, &schib);
> +	report(!cc, "STSCH cc == 0");
> +	report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is clear");
> +
> +	report_prefix_pop();
> +
> +	report_prefix_push("Bit 5 clear");
> +
> +	schib.pmcw.flags = old_pmcw_flags & ~BIT(15 - 5);
> +	cc = msch(test_device_sid, &schib);
> +	report(!cc, "MSCH cc == 0");
> +
> +	cc = stsch(test_device_sid, &schib);
> +	report(!cc, "STSCH cc == 0");
> +	report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is clear");
> +
> +	report_prefix_pop();
> +}
> +
>   static struct {
>   	const char *name;
>   	void (*func)(void);
> @@ -511,6 +583,8 @@ static struct {
>   	{ "msch", test_msch },
>   	{ "stcrw", test_stcrw },
>   	{ "ssch", test_ssch },
> +	{ "stsch", test_stsch },
> +	{ "pmcw bit 5 ignored", test_pmcw_bit5 },
>   	{ NULL, NULL }
>   };
>   

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Nico Boehr]

On Wed, 2022-02-23 at 16:39 +0100, Janosch Frank wrote:
> On 2/23/22 14:29, Nico Boehr wrote:
> > 
[...]
> >   
> > +static void test_stsch(void)
> > +{
> > 
[...]
> > +       report_prefix_push("Bit 47 in SID is zero");
> > +       expect_pgm_int();
> > +       stsch(0x0000ffff, &schib);
> > +       check_pgm_int_code(PGM_INT_CODE_OPERAND);
> > +       report_prefix_pop();
> 
> Add a comment:
> No matter if the multiple-subchannel-set facility is installed or
> not, 
> bit 47 always needs to be 1.

Will do.

> Do we have the MSS facility?

Not an IO expert, but it seems like it's enabled by QEMU in pc-
bios/s390-ccw/main.c, css_setup(). The comment suggests it's always
there.

> If yes, could we disable it to test the 32-47 == 0x0001 case?

I see ioinst_handle_chsc_sda() in QEMU to enable it. Disabling only
works with a full reset of the CSS (see css_reset()) which can be
triggered from a subsystem_reset(), which basically means we need to
IPL. I think that's not really viable or do you see any other way?

Halil, Pierre, can you confirm?

> 
> > +}
> > +
> > +static void test_pmcw_bit5(void)
> > +{
> > +       int cc;
> > +       uint16_t old_pmcw_flags;
> 
> I need a comment here for further reference since that behavior is 
> documented at the description of the schib and not where STSCH is
> described:
> According to architecture MSCH does ignore bit 5 of the second word
> but 
> STSCH will store bit 5 as zero.

Will add the comment above the function, OK?

> We could check if bits 0,1 and 6,7 are also zero but I'm not sure if 
> that's interesting since MSCH does not ignore those bits and should 
> result in an operand exception when trying to set them.

I already have a test in MSCH which checks for the operand exception.
It's simple enough to extend it to do a STSCH after the MSCH and check
the respective bits is clear. Will be added in v4.

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Halil Pasic]

On Wed, 23 Feb 2022 18:33:17 +0100
Nico Boehr <nrb@linux.ibm.com> wrote:

> On Wed, 2022-02-23 at 16:39 +0100, Janosch Frank wrote:
> > On 2/23/22 14:29, Nico Boehr wrote:  
> > >   
> [...]
> > >   
> > > +static void test_stsch(void)
> > > +{
> > >   
> [...]
> > > +       report_prefix_push("Bit 47 in SID is zero");
> > > +       expect_pgm_int();
> > > +       stsch(0x0000ffff, &schib);
> > > +       check_pgm_int_code(PGM_INT_CODE_OPERAND);
> > > +       report_prefix_pop();  
> > 
> > Add a comment:
> > No matter if the multiple-subchannel-set facility is installed or
> > not, 
> > bit 47 always needs to be 1.  
> 
> Will do.
> 
> > Do we have the MSS facility?  
> 
> Not an IO expert, but it seems like it's enabled by QEMU in pc-
> bios/s390-ccw/main.c, css_setup(). The comment suggests it's always
> there.
> 

AFAIR. The MSS facility is unconditionally implemented by QEMU thus
it is always indicated as installed, but lies dormant per default
and needs to be enabled.

The idea is that a non-enlightened OS would not enable the facility,
and thus effectively end up specifying zeros and using the
subchannel-set 0, and would observe no changes whatsoever compared
to running on a machine that does not have MSS facility installed.

Whether MSS is installed in some configuration or not can be detected
via the facility bit 47 of Store Channel-Subsystem Characteristics.

> > If yes, could we disable it to test the 32-47 == 0x0001 case?  
> 
> I see ioinst_handle_chsc_sda() in QEMU to enable it. Disabling only
> works with a full reset of the CSS (see css_reset()) which can be
> triggered from a subsystem_reset(), which basically means we need to
> IPL. I think that's not really viable or do you see any other way?
> 
> Halil, Pierre, can you confirm?

I don't think there is an other way, and there is usually no good reason
to attempt that. If your OS enables it is enlightened, and it won't
become non-enlightened. It is basically an opt-in. Eventually you may
want to IPL something different, and you are covered by the subsystem
reset.

The best way to test this would be to not enable the facility. I have
no idea if there is a way for a kvm-unit-test to accomplish that.

Regards,
Halil

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Pierre Morel]

On 2/23/22 16:39, Janosch Frank wrote:
> On 2/23/22 14:29, Nico Boehr wrote:
>> css_lib extensively uses STSCH, but two more cases deserve their own
>> tests:
>>
>> - unaligned address for SCHIB. We check for misalignment by 1 and 2
>>    bytes.
>> - channel not operational
>> - bit 47 in SID not set
>> - bit 5 of PMCW flags.
>>    As per the principles of operation, bit 5 of the PMCW flags shall be
>>    ignored by msch and always stored as zero by stsch.
>>
>>    Older QEMU versions require this bit to always be zero on msch,
>>    which is why this test may fail. A fix is available in QEMU master
>>    commit 2df59b73e086 ("s390x/css: fix PMCW invalid mask"). >
>> Here's the QEMU PMCW invalid mask fix: 
>> https://lists.nongnu.org/archive/html/qemu-s390x/2021-12/msg00100.html
>>
>> Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
>> ---
>>   s390x/css.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 74 insertions(+)
>>
>> diff --git a/s390x/css.c b/s390x/css.c
>> index a90a0cd64e2b..021eb12573c0 100644
>> --- a/s390x/css.c
>> +++ b/s390x/css.c
>> @@ -496,6 +496,78 @@ static void test_ssch(void)
>>       report_prefix_pop();
>>   }
>> +static void test_stsch(void)
>> +{
>> +    const int align_to = 4;
>> +    struct schib schib;
>> +    int cc;
>> +
>> +    if (!test_device_sid) {
>> +        report_skip("No device");
>> +        return;
>> +    }
>> +
>> +    report_prefix_push("Unaligned");
>> +    for (int i = 1; i < align_to; i *= 2) {
>> +        report_prefix_pushf("%d", i);
>> +
>> +        expect_pgm_int();
>> +        stsch(test_device_sid, (struct schib *)(alignment_test_page + 
>> i));
>> +        check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
>> +
>> +        report_prefix_pop();
>> +    }
>> +    report_prefix_pop();
>> +
>> +    report_prefix_push("Invalid subchannel number");
>> +    cc = stsch(0x0001ffff, &schib);
>> +    report(cc == 3, "Channel not operational");
>> +    report_prefix_pop();
>> +
>> +    report_prefix_push("Bit 47 in SID is zero");
>> +    expect_pgm_int();
>> +    stsch(0x0000ffff, &schib);
>> +    check_pgm_int_code(PGM_INT_CODE_OPERAND);
>> +    report_prefix_pop();
> 
> Add a comment:
> No matter if the multiple-subchannel-set facility is installed or not, 
> bit 47 always needs to be 1.
> 
> Do we have the MSS facility?

yes

> If yes, could we disable it to test the 32-47 == 0x0001 case?

AFAIK it is not enabled in the KVM unit tests
We are able to enable it, it could be done with CHSC tests.

> 
>> +}
>> +
>> +static void test_pmcw_bit5(void)
>> +{
>> +    int cc;
>> +    uint16_t old_pmcw_flags;
> 
> I need a comment here for further reference since that behavior is 
> documented at the description of the schib and not where STSCH is 
> described:
> According to architecture MSCH does ignore bit 5 of the second word but 
> STSCH will store bit 5 as zero.
> 
> 
> We could check if bits 0,1 and 6,7 are also zero but I'm not sure if 
> that's interesting since MSCH does not ignore those bits and should 
> result in an operand exception when trying to set them.
> 
> @Halil, @Pierre: Any opinions?


Yes we should check this.
We often do STSCH/MSCH in a row so I think it is interesting to check it.

> 
>> +
>> +    cc = stsch(test_device_sid, &schib);
>> +    if (cc) {
>> +        report_fail("stsch: sch %08x failed with cc=%d", 
>> test_device_sid, cc);
>> +        return;
>> +    }
>> +    old_pmcw_flags = schib.pmcw.flags;
>> +
>> +    report_prefix_push("Bit 5 set");
>> +
>> +    schib.pmcw.flags = old_pmcw_flags | BIT(15 - 5);
>> +    cc = msch(test_device_sid, &schib);
>> +    report(!cc, "MSCH cc == 0");
>> +
>> +    cc = stsch(test_device_sid, &schib);
>> +    report(!cc, "STSCH cc == 0");
>> +    report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is 
>> clear");
>> +
>> +    report_prefix_pop();
>> +
>> +    report_prefix_push("Bit 5 clear");
>> +
>> +    schib.pmcw.flags = old_pmcw_flags & ~BIT(15 - 5);
>> +    cc = msch(test_device_sid, &schib);
>> +    report(!cc, "MSCH cc == 0");
>> +
>> +    cc = stsch(test_device_sid, &schib);
>> +    report(!cc, "STSCH cc == 0");
>> +    report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is 
>> clear");
>> +
>> +    report_prefix_pop();
>> +}
>> +
>>   static struct {
>>       const char *name;
>>       void (*func)(void);
>> @@ -511,6 +583,8 @@ static struct {
>>       { "msch", test_msch },
>>       { "stcrw", test_stcrw },
>>       { "ssch", test_ssch },
>> +    { "stsch", test_stsch },
>> +    { "pmcw bit 5 ignored", test_pmcw_bit5 },
>>       { NULL, NULL }
>>   };
> 

-- 
Pierre Morel
IBM Lab Boeblingen

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Pierre Morel]

On 2/24/22 11:27, Pierre Morel wrote:
> 
> 
> On 2/23/22 16:39, Janosch Frank wrote:
>> On 2/23/22 14:29, Nico Boehr wrote:
>>> css_lib extensively uses STSCH, but two more cases deserve their own
>>> tests:
>>>
>>> - unaligned address for SCHIB. We check for misalignment by 1 and 2
>>>    bytes.
>>> - channel not operational
>>> - bit 47 in SID not set
>>> - bit 5 of PMCW flags.
>>>    As per the principles of operation, bit 5 of the PMCW flags shall be
>>>    ignored by msch and always stored as zero by stsch.
>>>
>>>    Older QEMU versions require this bit to always be zero on msch,
>>>    which is why this test may fail. A fix is available in QEMU master
>>>    commit 2df59b73e086 ("s390x/css: fix PMCW invalid mask"). >
>>> Here's the QEMU PMCW invalid mask fix: 
>>> https://lists.nongnu.org/archive/html/qemu-s390x/2021-12/msg00100.html
>>>
>>> Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
>>> ---
>>>   s390x/css.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 74 insertions(+)
>>>
>>> diff --git a/s390x/css.c b/s390x/css.c
>>> index a90a0cd64e2b..021eb12573c0 100644
>>> --- a/s390x/css.c
>>> +++ b/s390x/css.c
>>> @@ -496,6 +496,78 @@ static void test_ssch(void)
>>>       report_prefix_pop();
>>>   }
>>> +static void test_stsch(void)
>>> +{
>>> +    const int align_to = 4;
>>> +    struct schib schib;
>>> +    int cc;
>>> +
>>> +    if (!test_device_sid) {
>>> +        report_skip("No device");
>>> +        return;
>>> +    }
>>> +
>>> +    report_prefix_push("Unaligned");
>>> +    for (int i = 1; i < align_to; i *= 2) {
>>> +        report_prefix_pushf("%d", i);
>>> +
>>> +        expect_pgm_int();
>>> +        stsch(test_device_sid, (struct schib *)(alignment_test_page 
>>> + i));
>>> +        check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
>>> +
>>> +        report_prefix_pop();
>>> +    }
>>> +    report_prefix_pop();
>>> +
>>> +    report_prefix_push("Invalid subchannel number");
>>> +    cc = stsch(0x0001ffff, &schib);
>>> +    report(cc == 3, "Channel not operational");
>>> +    report_prefix_pop();
>>> +
>>> +    report_prefix_push("Bit 47 in SID is zero");
>>> +    expect_pgm_int();
>>> +    stsch(0x0000ffff, &schib);
>>> +    check_pgm_int_code(PGM_INT_CODE_OPERAND);
>>> +    report_prefix_pop();
>>
>> Add a comment:
>> No matter if the multiple-subchannel-set facility is installed or not, 
>> bit 47 always needs to be 1.
>>
>> Do we have the MSS facility?
> 
> yes
> 
>> If yes, could we disable it to test the 32-47 == 0x0001 case?
> 
> AFAIK it is not enabled in the KVM unit tests
> We are able to enable it, it could be done with CHSC tests.

I mean to check if it is enabled.

> 
>>
>>> +}
>>> +
>>> +static void test_pmcw_bit5(void)
>>> +{
>>> +    int cc;
>>> +    uint16_t old_pmcw_flags;
>>
>> I need a comment here for further reference since that behavior is 
>> documented at the description of the schib and not where STSCH is 
>> described:
>> According to architecture MSCH does ignore bit 5 of the second word 
>> but STSCH will store bit 5 as zero.
>>
>>
>> We could check if bits 0,1 and 6,7 are also zero but I'm not sure if 
>> that's interesting since MSCH does not ignore those bits and should 
>> result in an operand exception when trying to set them.
>>
>> @Halil, @Pierre: Any opinions?
> 
> 
> Yes we should check this.
> We often do STSCH/MSCH in a row so I think it is interesting to check it.
> 
>>
>>> +
>>> +    cc = stsch(test_device_sid, &schib);
>>> +    if (cc) {
>>> +        report_fail("stsch: sch %08x failed with cc=%d", 
>>> test_device_sid, cc);
>>> +        return;
>>> +    }
>>> +    old_pmcw_flags = schib.pmcw.flags;
>>> +
>>> +    report_prefix_push("Bit 5 set");
>>> +
>>> +    schib.pmcw.flags = old_pmcw_flags | BIT(15 - 5);
>>> +    cc = msch(test_device_sid, &schib);
>>> +    report(!cc, "MSCH cc == 0");
>>> +
>>> +    cc = stsch(test_device_sid, &schib);
>>> +    report(!cc, "STSCH cc == 0");
>>> +    report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is 
>>> clear");
>>> +
>>> +    report_prefix_pop();
>>> +
>>> +    report_prefix_push("Bit 5 clear");
>>> +
>>> +    schib.pmcw.flags = old_pmcw_flags & ~BIT(15 - 5);
>>> +    cc = msch(test_device_sid, &schib);
>>> +    report(!cc, "MSCH cc == 0");
>>> +
>>> +    cc = stsch(test_device_sid, &schib);
>>> +    report(!cc, "STSCH cc == 0");
>>> +    report(!(schib.pmcw.flags & BIT(15 - 5)), "STSCH PMCW Bit 5 is 
>>> clear");
>>> +
>>> +    report_prefix_pop();
>>> +}
>>> +
>>>   static struct {
>>>       const char *name;
>>>       void (*func)(void);
>>> @@ -511,6 +583,8 @@ static struct {
>>>       { "msch", test_msch },
>>>       { "stcrw", test_stcrw },
>>>       { "ssch", test_ssch },
>>> +    { "stsch", test_stsch },
>>> +    { "pmcw bit 5 ignored", test_pmcw_bit5 },
>>>       { NULL, NULL }
>>>   };
>>
> 

-- 
Pierre Morel
IBM Lab Boeblingen

Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH

[Halil Pasic]

On Wed, 23 Feb 2022 16:39:07 +0100
Janosch Frank <frankja@linux.ibm.com> wrote:

> We could check if bits 0,1 and 6,7 are also zero but I'm not sure if 
> that's interesting since MSCH does not ignore those bits and should 
> result in an operand exception when trying to set them.
> 
> @Halil, @Pierre: Any opinions?

IMHO more testing doesn't hurt. But I don't have clarity on some aspect
of how the architecture is extended. What I'm trying to say is: I'm not
100% certain these bits must stay 0 and no-semantics-defined forever.

Regards,
Halil

[kvm-unit-tests PATCH v3 7/8] s390x: Add tests for TSCH

[Nico Boehr]

TSCH has two special cases which need to be tested:

- unaligned address. We test for misalignment by 1 and 2 bytes.
- channel not operational
- bit 47 in SID not set

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.ibm.com>
---
 s390x/css.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/s390x/css.c b/s390x/css.c
index 021eb12573c0..b2e027c99848 100644
--- a/s390x/css.c
+++ b/s390x/css.c
@@ -568,6 +568,41 @@ static void test_pmcw_bit5(void)
 	report_prefix_pop();
 }
 
+static void test_tsch(void)
+{
+	const int align_to = 4;
+	struct irb irb;
+	int cc;
+
+	if (!test_device_sid) {
+		report_skip("No device");
+		return;
+	}
+
+	report_prefix_push("Unaligned");
+	for (int i = 1; i < align_to; i *= 2) {
+		report_prefix_pushf("%d", i);
+
+		expect_pgm_int();
+		tsch(test_device_sid, (struct irb *)(alignment_test_page + i));
+		check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+
+		report_prefix_pop();
+	}
+	report_prefix_pop();
+
+	report_prefix_push("Invalid subchannel number");
+	cc = tsch(0x0001ffff, &irb);
+	report(cc == 3, "Channel not operational");
+	report_prefix_pop();
+
+	report_prefix_push("Bit 47 in SID is zero");
+	expect_pgm_int();
+	tsch(0x0000ffff, &irb);
+	check_pgm_int_code(PGM_INT_CODE_OPERAND);
+	report_prefix_pop();
+}
+
 static struct {
 	const char *name;
 	void (*func)(void);
@@ -585,6 +620,7 @@ static struct {
 	{ "ssch", test_ssch },
 	{ "stsch", test_stsch },
 	{ "pmcw bit 5 ignored", test_pmcw_bit5 },
+	{ "tsch", test_tsch },
 	{ NULL, NULL }
 };
 
-- 
2.31.1

[kvm-unit-tests PATCH v3 8/8] s390x: Add EPSW test

[Nico Boehr]

EPSW is only intercepted in certain cases. One of these cases is if we
have a CRW pending and machine check interrupts are masked. This can be
achieved by issuing a RCHP on a valid channel path. This is why we need
the CSS lib and an IO device in this test and hence need to skip it
when not running under QEMU.

Three special cases deserve our attention:

- upper 32 bits of both operands are never modified,
- second operand is not modified if it is zero.
- when both operands are zero, bits 0-11 and 13-31 of the PSW are
  stored in r0.

We also verify we get the correct contents when the second operand is
zero. To do so, we save the data stored at the first operand in the
first case as a reference. As we don't mess with the PSW, the only thing
that might change is the Condition Code (CC) due to some instruction in
between, so we zero it out using zero_out_cc_from_epsw_op1().

This test must be fenced when running in non-QEMU.

Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
---
 s390x/Makefile      |   1 +
 s390x/epsw.c        | 113 ++++++++++++++++++++++++++++++++++++++++++++
 s390x/unittests.cfg |   4 ++
 3 files changed, 118 insertions(+)
 create mode 100644 s390x/epsw.c

diff --git a/s390x/Makefile b/s390x/Makefile
index a76b78e5a011..25449708da0d 100644
--- a/s390x/Makefile
+++ b/s390x/Makefile
@@ -27,6 +27,7 @@ tests += $(TEST_DIR)/edat.elf
 tests += $(TEST_DIR)/mvpg-sie.elf
 tests += $(TEST_DIR)/spec_ex-sie.elf
 tests += $(TEST_DIR)/firq.elf
+tests += $(TEST_DIR)/epsw.elf
 
 pv-tests += $(TEST_DIR)/pv-diags.elf
 
diff --git a/s390x/epsw.c b/s390x/epsw.c
new file mode 100644
index 000000000000..192115cf2fac
--- /dev/null
+++ b/s390x/epsw.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * EPSW Interception Tests
+ *
+ * Copyright IBM Corp. 2022
+ *
+ * Authors:
+ *  Nico Boehr <nrb@linux.ibm.com>
+ */
+#include <libcflat.h>
+#include <css.h>
+#include <vm.h>
+
+static uint32_t zero_out_cc_from_epsw_op1(uint32_t epsw_op1)
+{
+	return epsw_op1 & ~GENMASK(31 - 18, 31 - 20);
+}
+
+static void generate_crw(void)
+{
+	int test_device_sid = css_enumerate();
+	int cc, ret;
+
+	if (!(test_device_sid & SCHID_ONE)) {
+		report_fail("No I/O device found");
+		return;
+	}
+
+	cc = css_enable(test_device_sid, IO_SCH_ISC);
+	report(cc == 0, "Enable subchannel %08x", test_device_sid);
+
+	ret = css_generate_crw(test_device_sid);
+	if (ret)
+		report_fail("Couldn't generate CRW");
+}
+
+static void test_epsw(void)
+{
+	const uint64_t MAGIC1 = 0x1234567890abcdefUL;
+	const uint64_t MAGIC2 = 0xcafedeadbeeffaceUL;
+
+	uint64_t op1 = MAGIC1;
+	uint64_t op2 = MAGIC2;
+	uint32_t prev_epsw_op1;
+
+	/*
+	 * having machine check interrupts masked and pending CRW ensures
+	 * EPSW is intercepted under KVM
+	 */
+	generate_crw();
+
+	report_prefix_push("both operands given");
+	asm volatile(
+		"epsw %0, %1\n"
+		: "+&d" (op1), "+&a" (op2));
+	report(upper_32_bits(op1) == upper_32_bits(MAGIC1) &&
+	       upper_32_bits(op2) == upper_32_bits(MAGIC2),
+	       "upper 32 bits unmodified");
+	report(lower_32_bits(op1) != lower_32_bits(MAGIC1) &&
+	       lower_32_bits(op2) != lower_32_bits(MAGIC2),
+	       "lower 32 bits modified");
+	prev_epsw_op1 = zero_out_cc_from_epsw_op1(lower_32_bits(op1));
+	report_prefix_pop();
+
+	report_prefix_push("second operand 0");
+	op1 = MAGIC1;
+	op2 = MAGIC2;
+	asm volatile(
+		"	lgr 0,%[op2]\n"
+		"	epsw %[op1], 0\n"
+		"	lgr %[op2],0\n"
+		: [op2] "+&d" (op2), [op1] "+&a" (op1)
+		:
+		: "0");
+	report(upper_32_bits(op1) == upper_32_bits(MAGIC1),
+	       "upper 32 bits of first operand unmodified");
+	report(zero_out_cc_from_epsw_op1(lower_32_bits(op1)) == prev_epsw_op1,
+	       "first operand matches previous reading");
+	report(op2 == MAGIC2, "r0 unmodified");
+	report_prefix_pop();
+
+	report_prefix_push("both operands 0");
+	op1 = MAGIC1;
+	asm volatile(
+		"	lgr 0,%[op1]\n"
+		"	epsw 0, 0\n"
+		"	lgr %[op1],0\n"
+		: [op1] "+&d" (op1)
+		:
+		: "0");
+	report(upper_32_bits(op1) == upper_32_bits(MAGIC1),
+	       "upper 32 bits of first operand unmodified");
+	report(zero_out_cc_from_epsw_op1(lower_32_bits(op1)) == prev_epsw_op1,
+	       "first operand matches previous reading");
+	report_prefix_pop();
+}
+
+int main(int argc, char **argv)
+{
+	if (!vm_is_kvm() && !vm_is_tcg()) {
+		report_skip("Not running under QEMU");
+		goto done;
+	}
+
+	report_prefix_push("epsw");
+
+	test_epsw();
+
+done:
+	report_prefix_pop();
+
+	return report_summary();
+}
diff --git a/s390x/unittests.cfg b/s390x/unittests.cfg
index 8b148fe31ac0..aeb82246dddf 100644
--- a/s390x/unittests.cfg
+++ b/s390x/unittests.cfg
@@ -139,3 +139,7 @@ accel = tcg
 
 [sck]
 file = sck.elf
+
+[epsw]
+file = epsw.elf
+extra_params = -device virtio-net-ccw
-- 
2.31.1

Re: [kvm-unit-tests PATCH v3 0/8] s390x: Extend instruction interception tests

[Claudio Imbrenda]

On Wed, 23 Feb 2022 14:29:32 +0100
Nico Boehr <nrb@linux.ibm.com> wrote:

> This series extends the instruction interception tests for s390x.

looks good, I'll queue it, thanks

> 
> For most instructions, there is already coverage in existing tests, but they are
> not covering some failure cases, e.g. bad alignment. In this case, the existing
> tests were extended.
> 
> SCK was not under test anywhere yet, hence a new test file was added.
> 
> The EPSW test gets it's own file, too, because it requires a I/O device, more
> details in the respective commit. 
> 
> Changelog from v2:
> ----
> - Don't run the sck test under PV
> - Include commit of the QEMU PMCW fix in the MSCH and STSCH commit messages
> 
> Nico Boehr (8):
>   s390x: Add more tests for MSCH
>   s390x: Add test for PFMF low-address protection
>   s390x: Add sck tests
>   s390x: Add tests for STCRW
>   s390x: Add more tests for SSCH
>   s390x: Add more tests for STSCH
>   s390x: Add tests for TSCH
>   s390x: Add EPSW test
> 
>  lib/s390x/css.h     |  17 +++
>  lib/s390x/css_lib.c |  60 ++++++++++
>  s390x/Makefile      |   2 +
>  s390x/css.c         | 278 ++++++++++++++++++++++++++++++++++++++++++++
>  s390x/epsw.c        | 113 ++++++++++++++++++
>  s390x/pfmf.c        |  29 +++++
>  s390x/sck.c         | 134 +++++++++++++++++++++
>  s390x/unittests.cfg |   7 ++
>  8 files changed, 640 insertions(+)
>  create mode 100644 s390x/epsw.c
>  create mode 100644 s390x/sck.c
>