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Mon, 06 Jan 2025 08:28:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IFhi2SYCIWSDt6cklfzahC0bZr7S4U+xeNewvxNt7RadojvE0j28xssj9KSgjAMXq4it3yS9g== X-Received: by 2002:a05:6602:2dc2:b0:847:5b61:636c with SMTP id ca18e2360f4ac-8499e4c8cf8mr1605755939f.2.1736180926206; Mon, 06 Jan 2025 08:28:46 -0800 (PST) Received: from redhat.com ([38.15.36.11]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-8498d8eb32asm891093239f.42.2025.01.06.08.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2025 08:28:45 -0800 (PST) Date: Mon, 6 Jan 2025 11:28:40 -0500 From: Alex Williamson To: Ramesh Thomas Cc: jgg@ziepe.ca, schnelle@linux.ibm.com, gbayer@linux.ibm.com, kvm@vger.kernel.org, linux-s390@vger.kernel.org, ankita@nvidia.com, yishaih@nvidia.com, pasic@linux.ibm.com, julianr@linux.ibm.com, bpsegal@us.ibm.com, kevin.tian@intel.com, cho@microsoft.com Subject: Re: [PATCH v3 0/2] Extend 8-byte PCI load/store support to x86 arch Message-ID: <20250106112840.423340ae.alex.williamson@redhat.com> In-Reply-To: <20241210131938.303500-1-ramesh.thomas@intel.com> References: <20241210131938.303500-1-ramesh.thomas@intel.com> Organization: Red Hat Precedence: bulk X-Mailing-List: linux-s390@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 10 Dec 2024 05:19:36 -0800 Ramesh Thomas wrote: > This patch series extends the recently added 8-byte PCI load/store > support to the x86 architecture. > > Refer patch series adding above support: > https://lore.kernel.org/all/20240522150651.1999584-1-gbayer@linux.ibm.com/ > > The 8-byte implementations are enclosed inside #ifdef checks of the > macros "ioread64" and "iowrite64". These macros don't get defined if > CONFIG_GENERIC_IOMAP is defined. CONFIG_GENERIC_IOMAP gets defined for > x86 and hence the macros are undefined. Due to this the 8-byte support > was not enabled for x86 architecture. > > To resolve this, include the header file io-64-nonatomic-lo-hi.h that > maps the ioread64 and iowrite64 macros to a generic implementation in > lib/iomap.c. This was the intention of defining CONFIG_GENERIC_IOMAP. > > Tested using a pass-through PCI device bound to vfio-pci driver and > doing BAR reads and writes that trigger calls to > vfio_pci_core_do_io_rw() that does the 8-byte reads and writes. > > Patch history: > v3: Do not add the check for CONFIG_64BIT and only remove the checks for > ioread64 and iowrite64. > > v2: Based on Jason's feedback moved #include io-64-nonatomic-lo-hi.h > to vfio_pci_rdwr.c and replaced #ifdef checks of iowrite64 and ioread64 > macros with checks for CONFIG_64BIT. > > https://lore.kernel.org/all/20240522232125.548643-1-ramesh.thomas@intel.com/ > https://lore.kernel.org/all/20240524140013.GM69273@ziepe.ca/ > https://lore.kernel.org/all/bfb273b2-fc5e-4a8b-a40d-56996fc9e0af@intel.com/ > > Ramesh Thomas (2): > vfio/pci: Enable iowrite64 and ioread64 for vfio pci > vfio/pci: Remove #ifdef iowrite64 and #ifdef ioread64 > > drivers/vfio/pci/vfio_pci_rdwr.c | 13 +------------ > 1 file changed, 1 insertion(+), 12 deletions(-) > Applied to vfio next branch for v6.14. Thanks, Alex