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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45e7c22d8b7sm24718459f8f.6.2026.05.20.05.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 05:43:19 -0700 (PDT) Date: Wed, 20 May 2026 13:43:17 +0100 From: David Laight To: Heiko Carstens Cc: Alexander Gordeev , Sven Schnelle , Vasily Gorbik , Christian Borntraeger , Juergen Christ , Peter Zijlstra , Yang Shi , Shrikanth Hegde , linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Subject: Re: [PATCH v3 1/9] s390/alternatives: Add new ALT_TYPE_PERCPU type Message-ID: <20260520134317.778dc094@pumpkin> In-Reply-To: <20260520092243.264847-2-hca@linux.ibm.com> References: <20260520092243.264847-1-hca@linux.ibm.com> <20260520092243.264847-2-hca@linux.ibm.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-s390@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 20 May 2026 11:22:35 +0200 Heiko Carstens wrote: > The upcoming percpu section code uses two mviy instructions to guard the > beginning and end of a percpu code section. > > The first mviy instruction writes the register number, which contains the > percpu address to lowcore. This indicates both the beginning of a percpu > code section and which register contains the percpu address. > > During compile time the mviy instruction is generated in a way that its > base register contains the percpu register, and the immediate field is > zero. This needs to be patched so that the base register is zero, and the > immediate field contains the register number. For example > > 101424: eb 00 23 c0 00 52 mviy 960(%r2),0 > > needs to be patched to > > 101424: eb 20 03 c0 00 52 mviy 960(%r0),2 I'm sure it is possible get the preprocessor to extract the register number for you. The exception table logic almost certainly already does it. (The x86 version certainly does - and that is far less trivial.) -- David > > Provide a new ALT_TYPE_PERCPU alternative type which handles this specific > instruction patching. In addition it also handles the relocated lowcore > case, where the displacement of the mviy instruction has a different value.