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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490923613d0sm95054665e9.3.2026.05.28.13.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 13:34:07 -0700 (PDT) Date: Thu, 28 May 2026 21:34:05 +0100 From: David Laight To: Yang Shi Cc: Heiko Carstens , Alexander Gordeev , Sven Schnelle , Vasily Gorbik , Christian Borntraeger , Juergen Christ , "Christoph Lameter (Ampere)" , Peter Zijlstra , Shrikanth Hegde , linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Subject: Re: [PATCH v3 0/9] s390: Improve this_cpu operations Message-ID: <20260528213406.134cf354@pumpkin> In-Reply-To: <37aa12be-f3ee-4b6d-8fcc-33ccdec2725b@os.amperecomputing.com> References: <20260520092243.264847-1-hca@linux.ibm.com> <9d503c6f-5641-4b28-998e-01e38b3622a9@os.amperecomputing.com> <20260520233409.0683f595@pumpkin> <20260521103742.9603C8c-hca@linux.ibm.com> <5158d4e8-19a7-4f60-b2fd-bc6bab22baf0@os.amperecomputing.com> <20260522091805.18098A5c-hca@linux.ibm.com> <20260528100346.1e790a53@pumpkin> <37aa12be-f3ee-4b6d-8fcc-33ccdec2725b@os.amperecomputing.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-s390@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 28 May 2026 12:19:43 -0700 Yang Shi wrote: > On 5/28/26 2:03 AM, David Laight wrote: > > On Wed, 27 May 2026 16:44:31 -0700 > > Yang Shi wrote: > > > >> On 5/22/26 2:18 AM, Heiko Carstens wrote: > > ... > >>> It is amazing to see the performance improvements you see on arm64, however > >>> I believe that is mainly because of the large amount of code which is > >>> generated by the arm64 implementations of the preempt primitives > >>> __preempt_count_add() and __preempt_count_dec_and_test(). > >> Yes, we need 4 instructions on ARM64 for disabling/enabling preempt (one > >> instruction is used to load current pointer, the other 3 instructions > >> are used to RMW preempt_count). So I can remove 8 instructions in total > >> for a single this_cpu ops. That's a lot. Given this_cpu ops are heavily > >> used in kernel, we end up running fewer instructions and having better > >> icache hit rate, the better icache hit rate also helps reduce cross node > >> traffic for 2-socket system. > > Is 'current' kept in a cpu hardware register? > > Yes, sp_el0. But it is a special register, we need move it to a general > register before any ARM64 instructions can access it. That is what I thought. (Hmm... isn't that the userspace stack register?) > > > With the process switch code updating current->per_cpu_data. > > > > That might mean that you can access per-cpu data without disabling > > preemption (for single ops) using the same technique as s390. > > So something like: > > mov %ra, current > > movb per_cpu_reg(%ra), $b > > mov %rb, per_cpu_data(%ra) > > // per-cpu access using %rb, process switch code will update %rb > > movb per_cpu_reg(%ra), $255 > > > > An add will need to use a cmpxchg loop. > > For simplicity use a fixed register for %rb. > > TBH, I can't say I fully understand what you proposed. But it sounds > like this one > https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/commit/?id=84ee5f23f93d4a650e828f831da9ed29c54623c5 Not really, although it does describe one way to do an atomic add. For things like per-cpu stats you don't really care if the 'wrong' stats are changed, but the R and W (of the RMW) need to go to the same address. That proposal reserved a 'general register' for the per-cpu data all the time. Like the s390 code this all started with, I'm suggesting that the code tells the context switch code that a specific register contains the base of the per-cpu data, on context switch that register is changed to be the base address of the per-cpu data for the new cpu. So outside of the code accessing per-cpu data the register can be used normally. I don't think you need to look at the opcode if the process switch (the s390 code did), even checking that %rb (above) contains the per-cpu data address is really optional. I suggested using a fixed register meaning 'always use the same register' to save the difficultly of generating $n from %rn. -- David > > Thanks, > Yang > > > > > -- David >