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Tue, 14 Mar 2023 16:41:24 +0000 (GMT) Message-ID: <3976942b40bfb2c2a222d251db1629df7b6819c2.camel@linux.ibm.com> Subject: Re: [kvm-unit-tests PATCH v2 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address From: Nina Schoetterl-Glausch To: Claudio Imbrenda Cc: Thomas Huth , Janosch Frank , David Hildenbrand , kvm@vger.kernel.org, linux-s390@vger.kernel.org Date: Tue, 14 Mar 2023 17:41:24 +0100 In-Reply-To: <20230314162526.519364c5@p-imbrenda> References: <20230221174822.1378667-1-nsg@linux.ibm.com> <20230221174822.1378667-4-nsg@linux.ibm.com> <20230314162526.519364c5@p-imbrenda> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: lFYEoJIOjkbCT2jk0c_8sf6ugFPywgg7 X-Proofpoint-ORIG-GUID: Nz2mEHJxoAnEJqDncOc9TEJPlC4r8l0i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-14_10,2023-03-14_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303140129 Precedence: bulk List-ID: X-Mailing-List: linux-s390@vger.kernel.org On Tue, 2023-03-14 at 16:25 +0100, Claudio Imbrenda wrote: > On Tue, 21 Feb 2023 18:48:22 +0100 > Nina Schoetterl-Glausch wrote: >=20 > > The EXECUTE instruction executes the instruction at the given target > > address. This address must be halfword aligned, otherwise a > > specification exception occurs. > > Add a test for this. > >=20 > > Signed-off-by: Nina Schoetterl-Glausch > > --- > > s390x/spec_ex.c | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > >=20 > > diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c > > index a26c56aa..dd097f9b 100644 > > --- a/s390x/spec_ex.c > > +++ b/s390x/spec_ex.c > > @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void) > > return 0; > > } > > =20 > > +static int odd_ex_target(void) > > +{ > > + uint64_t pre_target_addr; > > + int to =3D 0, from =3D 0x0dd; > > + > > + asm volatile ( ".pushsection .rodata\n" >=20 > and this should go in a .text.something subsection, as we discussed > offline Yes. >=20 > > + "pre_odd_ex_target:\n" >=20 > shouldn't the label be after the align? No, larl needs an aligned address, and the ex below adds 1. That's why it has the pre_ prefix, it's not the ex target itself. >=20 > > + " .balign 2\n" >=20 > (i.e. here) >=20 > > + " . =3D . + 1\n" > > + " lr %[to],%[from]\n" > > + " .popsection\n" > > + > > + " larl %[pre_target_addr],pre_odd_ex_target\n" > > + " ex 0,1(%[pre_target_addr])\n" > > + : [pre_target_addr] "=3D&a" (pre_target_addr), > > + [to] "+d" (to) > > + : [from] "d" (from) > > + ); > > + > > + assert((pre_target_addr + 1) & 1); > > + report(to !=3D from, "did not perform ex with odd target"); > > + return 0; > > +} > > + > > static int bad_alignment(void) > > { > > uint32_t words[5] __attribute__((aligned(16))); > > @@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_trigger= s[] =3D { > > { "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw }, > > { "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_inva= lid_psw }, > > { "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw }, > > + { "odd_ex_target", &odd_ex_target, true, NULL }, > > { "bad_alignment", &bad_alignment, true, NULL }, > > { "not_even", ¬_even, true, NULL }, > > { NULL, NULL, false, NULL }, >=20