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(p200300cbc708180042bd3cacd22a3c62.dip0.t-ipconnect.de. [2003:cb:c708:1800:42bd:3cac:d22a:3c62]) by smtp.gmail.com with ESMTPSA id c7-20020a5d4f07000000b00203db8f13c6sm466545wru.75.2022.03.15.10.14.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:14:06 -0700 (PDT) Message-ID: <51afa7a7-15c5-8769-78db-ed2d134792f4@redhat.com> Date: Tue, 15 Mar 2022 18:14:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v1 5/7] s390/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Content-Language: en-US From: David Hildenbrand To: Gerald Schaefer Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Catalin Marinas , Will Deacon , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-6-david@redhat.com> <20220315172102.771bd2cf@thinkpad> <8b13b6c0-78d4-48e3-06f0-ec0680d013a9@redhat.com> <55b6b582-51ca-b869-2055-674fe4c563e6@redhat.com> Organization: Red Hat In-Reply-To: <55b6b582-51ca-b869-2055-674fe4c563e6@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-s390@vger.kernel.org On 15.03.22 18:12, David Hildenbrand wrote: > On 15.03.22 17:58, David Hildenbrand wrote: >> >>>> This would mean that it is not OK to have bit 52 not zero for swap PTEs. >>>> But if I read the POP correctly, all bits except for the DAT-protection >>>> would be ignored for invalid PTEs, so maybe this comment needs some update >>>> (for both bits 52 and also 55). >>>> >>>> Heiko might also have some more insight. >>> >>> Indeed, I wonder why we should get a specification exception when the >>> PTE is invalid. I'll dig a bit into the PoP. >> >> SA22-7832-12 6-46 ("Translation-Specification Exception") is clearer >> >> "The page-table entry used for the translation is >> valid, and bit position 52 does not contain zero." >> >> "The page-table entry used for the translation is >> valid, EDAT-1 does not apply, the instruction-exe- >> cution-protection facility is not installed, and bit >> position 55 does not contain zero. It is model >> dependent whether this condition is recognized." >> > > I wonder if the following matches reality: > > diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h > index 008a6c856fa4..6a227a8c3712 100644 > --- a/arch/s390/include/asm/pgtable.h > +++ b/arch/s390/include/asm/pgtable.h > @@ -1669,18 +1669,16 @@ static inline int has_transparent_hugepage(void) > /* > * 64 bit swap entry format: > * A page-table entry has some bits we have to treat in a special way. > - * Bits 52 and bit 55 have to be zero, otherwise a specification > - * exception will occur instead of a page translation exception. The > - * specification exception has the bad habit not to store necessary > - * information in the lowcore. > * Bits 54 and 63 are used to indicate the page type. > * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 > - * This leaves the bits 0-51 and bits 56-62 to store type and offset. > - * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 > - * for the offset. > - * | offset |01100|type |00| > + * | offset |XX1XX|type |S0| > * |0000000000111111111122222222223333333333444444444455|55555|55566|66| > * |0123456789012345678901234567890123456789012345678901|23456|78901|23| > + * > + * Bits 0-51 store the offset. > + * Bits 57-62 store the type. ^ 57-61, I should stop working for today :) -- Thanks, David / dhildenb