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Wed, 23 Feb 2022 17:33:17 +0000 (GMT) Message-ID: <99ec1cf03d17b3de2d47c497882f091f922713bf.camel@linux.ibm.com> Subject: Re: [kvm-unit-tests PATCH v3 6/8] s390x: Add more tests for STSCH From: Nico Boehr To: Janosch Frank , kvm@vger.kernel.org, linux-s390@vger.kernel.org Cc: imbrenda@linux.ibm.com, Pierre Morel , Halil Pasic , thuth@redhat.com, david@redhat.com Date: Wed, 23 Feb 2022 18:33:17 +0100 In-Reply-To: <04daca6a-5863-d205-ea98-096163a2296a@linux.ibm.com> References: <20220223132940.2765217-1-nrb@linux.ibm.com> <20220223132940.2765217-7-nrb@linux.ibm.com> <04daca6a-5863-d205-ea98-096163a2296a@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.42.4 (3.42.4-1.fc35) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: YGgnOs_t1BU2zagkI2kXfiwjHNxT01oX X-Proofpoint-GUID: 67LIQehrSHAjKCugolYGfPgZq0TF2Vo5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-23_09,2022-02-23_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 mlxscore=0 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202230100 Precedence: bulk List-ID: X-Mailing-List: linux-s390@vger.kernel.org On Wed, 2022-02-23 at 16:39 +0100, Janosch Frank wrote: > On 2/23/22 14:29, Nico Boehr wrote: > > [...] > >   > > +static void test_stsch(void) > > +{ > > [...] > > +       report_prefix_push("Bit 47 in SID is zero"); > > +       expect_pgm_int(); > > +       stsch(0x0000ffff, &schib); > > +       check_pgm_int_code(PGM_INT_CODE_OPERAND); > > +       report_prefix_pop(); > > Add a comment: > No matter if the multiple-subchannel-set facility is installed or > not, > bit 47 always needs to be 1. Will do. > Do we have the MSS facility? Not an IO expert, but it seems like it's enabled by QEMU in pc- bios/s390-ccw/main.c, css_setup(). The comment suggests it's always there. > If yes, could we disable it to test the 32-47 == 0x0001 case? I see ioinst_handle_chsc_sda() in QEMU to enable it. Disabling only works with a full reset of the CSS (see css_reset()) which can be triggered from a subsystem_reset(), which basically means we need to IPL. I think that's not really viable or do you see any other way? Halil, Pierre, can you confirm? > > > +} > > + > > +static void test_pmcw_bit5(void) > > +{ > > +       int cc; > > +       uint16_t old_pmcw_flags; > > I need a comment here for further reference since that behavior is > documented at the description of the schib and not where STSCH is > described: > According to architecture MSCH does ignore bit 5 of the second word > but > STSCH will store bit 5 as zero. Will add the comment above the function, OK? > We could check if bits 0,1 and 6,7 are also zero but I'm not sure if > that's interesting since MSCH does not ignore those bits and should > result in an operand exception when trying to set them. I already have a test in MSCH which checks for the operand exception. It's simple enough to extend it to do a STSCH after the MSCH and check the respective bits is clear. Will be added in v4.