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Fri, 1 Aug 2025 09:25:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C9.mail.protection.outlook.com (10.167.240.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 1 Aug 2025 09:25:53 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 3C3FE4126FFC; Fri, 1 Aug 2025 17:25:52 +0800 (CST) Message-ID: <9a155e45-f723-4eec-81d3-2547bfe9a4e9@cixtech.com> Date: Fri, 1 Aug 2025 17:25:51 +0800 Precedence: bulk X-Mailing-List: linux-s390@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: Fix endianness issues in pci_bus_read_config() To: Manivannan Sadhasivam , Arnd Bergmann Cc: Bjorn Helgaas , Gerd Bayer , Hans Zhang <18255117159@163.com>, bhelgaas@google.com, Alexander Gordeev , Christian Borntraeger , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , jingoohan1@gmail.com, =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, linux-next , linux-pci@vger.kernel.org, Lorenzo Pieralisi , Rob Herring , Niklas Schnelle , ilpo.jarvinen@linux.intel.com, geert@linux-m68k.org References: <20250731183944.GA3424583@bhelgaas> <6e34b4af-dff9-4360-b3da-c95ca7c740c9@app.fastmail.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2025 09:25:53.3365 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49904621-939e-4218-27f1-08ddd0dd69a9 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C9.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB5240 On 2025/8/1 16:18, Manivannan Sadhasivam wrote: > EXTERNAL EMAIL > > On Thu, Jul 31, 2025 at 09:01:17PM GMT, Arnd Bergmann wrote: >> On Thu, Jul 31, 2025, at 20:39, Bjorn Helgaas wrote: >>> On Thu, Jul 31, 2025 at 07:38:58PM +0200, Gerd Bayer wrote: >>>> >>>> - if (size == 1) >>>> - return pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); >>>> - else if (size == 2) >>>> - return pci_bus_read_config_word(bus, devfn, where, (u16 *)val); >>>> - else if (size == 4) >>>> - return pci_bus_read_config_dword(bus, devfn, where, val); >>>> - else >>>> - return PCIBIOS_BAD_REGISTER_NUMBER; >>>> + if (size == 1) { >>>> + rc = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); >>>> +#if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) >>>> + *val = ((*val >> 24) & 0xff); >>>> +#endif >>> >>> Yeah, this is all pretty ugly. Obviously the previous code in >>> __pci_find_next_cap_ttl() didn't need this. My guess is that was >>> because the destination for the read data was always the correct type >>> (u8/u16/u32), but here we always use a u32 and cast it to the >>> appropriate type. Maybe we can use the correct types here instead of >>> the casts? >> >> Agreed, the casts here just add more potential for bugs. >> > > Ack. Missed the obvious issue during review. > >> The pci_bus_read_config() interface itself may have been a >> mistake, can't the callers just use the underlying helpers >> directly? >> > > They can! Since the callers of this API is mostly the macros, we can easily > implement the logic to call relevant accessors based on the requested size. > > Hans, could you please respin the series based the feedback since the series is > dropped for 6.17. > Dear all, I am once again deeply sorry for the problems that occurred in this series. I only test pulling the ARM platform. Thank you very much, Gerd, for reporting the problem. Thank you all for your discussions and suggestions for revision. Hi Mani, Geert provided a solution. My patch based on this is as follows. Please check if there are any problems. https://lore.kernel.org/linux-pci/CAMuHMdVwFeV46oCid_sMHjXfP+yyGTpBfs9t3uaa=wRxNcSOAQ@mail.gmail.com/ Also, please ask Gerd to help test whether it works properly. Thank you very much. If there are no issues, am I sending the new version? Can this series of pacth 0001 be directly replaced? The patch is as follows: diff --git a/drivers/pci/access.c b/drivers/pci/access.c index ba66f55d2524..2bfd8fc1c0f5 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -89,15 +89,25 @@ int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size, u32 *val) { struct pci_bus *bus = priv; + int rc; + + if (size == 1) { + u8 byte; + + rc = pci_bus_read_config_byte(bus, devfn, where, &byte); + *val = byte; + } else if (size == 2) { + u16 word; + + rc = pci_bus_read_config_word(bus, devfn, where, &word); + *val = word; + } else if (size == 4) { + rc = pci_bus_read_config_dword(bus, devfn, where, val); + } else { + rc = PCIBIOS_BAD_REGISTER_NUMBER; + } - if (size == 1) - return pci_bus_read_config_byte(bus, devfn, where, (u8 *)val); - else if (size == 2) - return pci_bus_read_config_word(bus, devfn, where, (u16 *)val); - else if (size == 4) - return pci_bus_read_config_dword(bus, devfn, where, val); - else - return PCIBIOS_BAD_REGISTER_NUMBER; + return rc; } int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, Best regards, Hans