From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 1 Feb 2021 13:44:34 +0100 From: Peter Zijlstra Subject: Re: [RFC 00/20] TLB batching consolidation and enhancements Message-ID: References: <20210131001132.3368247-1-namit@vmware.com> <1612063149.2awdsvvmhj.astroid@bobo.none> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: List-ID: To: Nadav Amit Cc: Nicholas Piggin , LKML , Linux-MM , Andrea Arcangeli , Andrew Morton , Dave Hansen , "linux-csky@vger.kernel.org" , linuxppc-dev , linux-s390 , Andy Lutomirski , Mel Gorman , Thomas Gleixner , Will Deacon , X86 ML , Yu Zhao On Sun, Jan 31, 2021 at 07:57:01AM +0000, Nadav Amit wrote: > > On Jan 30, 2021, at 7:30 PM, Nicholas Piggin wrote: > > I'll go through the patches a bit more closely when they all come > > through. Sparc and powerpc of course need the arch lazy mode to get > > per-page/pte information for operations that are not freeing pages, > > which is what mmu gather is designed for. > > IIUC you mean any PTE change requires a TLB flush. Even setting up a new PTE > where no previous PTE was set, right? These are the HASH architectures. Their hardware doesn't walk the page-tables, but it consults a hash-table to resolve page translations. They _MUST_ flush the entries under the PTL to avoid ever seeing conflicting information, which will make them really unhappy. They can do this because they have TLBI broadcast. There's a few more details I'm sure, but those seem to have slipped from my mind.