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(p200300cbc7044900849bf76e5e1fff95.dip0.t-ipconnect.de. [2003:cb:c704:4900:849b:f76e:5e1f:ff95]) by smtp.gmail.com with ESMTPSA id g10-20020a5d46ca000000b00203fd86e198sm7209759wrs.96.2022.03.21.08.07.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Mar 2022 08:07:50 -0700 (PDT) Message-ID: Date: Mon, 21 Mar 2022 16:07:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Content-Language: en-US To: Will Deacon , Catalin Marinas Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> <20220321143802.GC11145@willie-the-truck> From: David Hildenbrand Organization: Red Hat In-Reply-To: <20220321143802.GC11145@willie-the-truck> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-s390@vger.kernel.org On 21.03.22 15:38, Will Deacon wrote: > On Wed, Mar 16, 2022 at 06:27:01PM +0000, Catalin Marinas wrote: >> On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: >>> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h >>> index b1e1b74d993c..62e0ebeed720 100644 >>> --- a/arch/arm64/include/asm/pgtable-prot.h >>> +++ b/arch/arm64/include/asm/pgtable-prot.h >>> @@ -14,6 +14,7 @@ >>> * Software defined PTE bits definition. >>> */ >>> #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ >>> +#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */ >> >> I think we can use bit 1 here. >> >>> @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, >>> /* >>> * Encode and decode a swap entry: >>> * bits 0-1: present (must be zero) >>> - * bits 2-7: swap type >>> + * bits 2: remember PG_anon_exclusive >>> + * bits 3-7: swap type >>> * bits 8-57: swap offset >>> * bit 58: PTE_PROT_NONE (must be zero) >> >> I don't remember exactly why we reserved bits 0 and 1 when, from the >> hardware perspective, it's sufficient for bit 0 to be 0 and the whole >> pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd >> level, it's a huge page) but we shouldn't check for this on a swap >> entry. > > I'm a little worried that when we're dealing with huge mappings at the > PMD level we might lose the ability to distinguish them from a pte-level > mapping with this new flag set if we use bit 1. A similar issue to this > was fixed a long time ago by 59911ca4325d ("ARM64: mm: Move PTE_PROT_NONE > bit") when we used to use bit 1 for PTE_PROT_NONE. > > Is something like: > > pmd_to_swp_entry(swp_entry_to_pmd(pmd)); Note that __HAVE_ARCH_PTE_SWP_EXCLUSIVE currently only applies to actual swap entries, not non-swap entries (migration, hwpoison, ...). So it really only applies to PTEs -- PMDs are not applicable. So the example you gave cannot possibly have that bit set. From what I understand, it should be fine. But I have no real preference: I can also just stick to the original patch, whatever you prefer. Thanks! -- Thanks, David / dhildenb