From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-2.mimecast.com ([207.211.31.81]:22295 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726157AbgDUQQQ (ORCPT ); Tue, 21 Apr 2020 12:16:16 -0400 Subject: Re: [kvm-unit-tests PATCH v5 02/10] s390x: Use PSW bits definitions in cstart References: <1582200043-21760-1-git-send-email-pmorel@linux.ibm.com> <1582200043-21760-3-git-send-email-pmorel@linux.ibm.com> From: David Hildenbrand Message-ID: Date: Tue, 21 Apr 2020 18:16:06 +0200 MIME-Version: 1.0 In-Reply-To: <1582200043-21760-3-git-send-email-pmorel@linux.ibm.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-s390-owner@vger.kernel.org List-ID: To: Pierre Morel , kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, thuth@redhat.com, cohuck@redhat.com On 20.02.20 13:00, Pierre Morel wrote: > This patch defines the PSW bits EA/BA used to initialize the PSW masks > for exceptions. > > Since some PSW mask definitions exist already in arch_def.h we add these > definitions there. > We move all PSW definitions together and protect assembler code against > C syntax. > > Signed-off-by: Pierre Morel > --- > lib/s390x/asm/arch_def.h | 15 +++++++++++---- > s390x/cstart64.S | 15 ++++++++------- > 2 files changed, 19 insertions(+), 11 deletions(-) > > diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h > index 15a4d49..69a8256 100644 > --- a/lib/s390x/asm/arch_def.h > +++ b/lib/s390x/asm/arch_def.h > @@ -10,15 +10,21 @@ > #ifndef _ASM_S390X_ARCH_DEF_H_ > #define _ASM_S390X_ARCH_DEF_H_ > > +#define PSW_MASK_EXT 0x0100000000000000UL > +#define PSW_MASK_DAT 0x0400000000000000UL > +#define PSW_MASK_PSTATE 0x0001000000000000UL > +#define PSW_MASK_BA 0x0000000080000000UL > +#define PSW_MASK_EA 0x0000000100000000UL > + > +#define PSW_EXCEPTION_MASK (PSW_MASK_EA|PSW_MASK_BA) > + > +#ifndef __ASSEMBLER__ > + > struct psw { > uint64_t mask; > uint64_t addr; > }; > > -#define PSW_MASK_EXT 0x0100000000000000UL > -#define PSW_MASK_DAT 0x0400000000000000UL > -#define PSW_MASK_PSTATE 0x0001000000000000UL > - > #define CR0_EXTM_SCLP 0X0000000000000200UL > #define CR0_EXTM_EXTC 0X0000000000002000UL > #define CR0_EXTM_EMGC 0X0000000000004000UL > @@ -297,4 +303,5 @@ static inline uint32_t get_prefix(void) > return current_prefix; > } > > +#endif /* not __ASSEMBLER__ */ > #endif > diff --git a/s390x/cstart64.S b/s390x/cstart64.S > index 45da523..2885a36 100644 > --- a/s390x/cstart64.S > +++ b/s390x/cstart64.S > @@ -12,6 +12,7 @@ > */ > #include > #include > +#include > > .section .init > > @@ -214,19 +215,19 @@ svc_int: > > .align 8 > reset_psw: > - .quad 0x0008000180000000 > + .quad PSW_EXCEPTION_MASK > initial_psw: > - .quad 0x0000000180000000, clear_bss_start > + .quad PSW_EXCEPTION_MASK, clear_bss_start > pgm_int_psw: > - .quad 0x0000000180000000, pgm_int > + .quad PSW_EXCEPTION_MASK, pgm_int > ext_int_psw: > - .quad 0x0000000180000000, ext_int > + .quad PSW_EXCEPTION_MASK, ext_int > mcck_int_psw: > - .quad 0x0000000180000000, mcck_int > + .quad PSW_EXCEPTION_MASK, mcck_int > io_int_psw: > - .quad 0x0000000180000000, io_int > + .quad PSW_EXCEPTION_MASK, io_int > svc_int_psw: > - .quad 0x0000000180000000, svc_int > + .quad PSW_EXCEPTION_MASK, svc_int > initial_cr0: > /* enable AFP-register control, so FP regs (+BFP instr) can be used */ > .quad 0x0000000000040000 > Reviewed-by: David Hildenbrand -- Thanks, David / dhildenb