From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jingoo Han Subject: Re: [PATCH V5] pci: exynos: split into two parts such as Synopsys part and Exynos part Date: Wed, 07 Aug 2013 13:13:42 +0900 Message-ID: <002501ce9324$8066f5a0$8134e0e0$@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-path: Content-language: ko Sender: linux-kernel-owner@vger.kernel.org To: 'Bjorn Helgaas' Cc: linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, 'Kukjin Kim' , 'Pratyush Anand' , 'Mohit KUMAR' , 'Arnd Bergmann' , 'Sean Cross' , 'Kishon Vijay Abraham I' , 'Thierry Reding' , 'SRIKANTH TUMKUR SHIVANAND' , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jingoo Han List-Id: linux-samsung-soc@vger.kernel.org On Wednesday, July 31, 2013 5:14 PM, Jingoo Han wrote: > Exynos PCIe IP consists of Synopsys specific part and Exynos > specific part. Only core block is a Synopsys designware part; > other parts are Exynos specific. > Also, the Synopsys designware part can be shared with other > platforms; thus, it can be split two parts such as Synopsys > designware part and Exynos specific part. > > Signed-off-by: Jingoo Han > Cc: Pratyush Anand > Cc: Mohit KUMAR Hi Bjorn Helgaas, There is no comment for last 2 weeks. Will you accept this patch? Best regards, Jingoo Han > --- > Changes since v4: > - fixed section mismatch warnings > - fixed sparse warnings > > .../devicetree/bindings/pci/designware-pcie.txt | 3 + > arch/arm/boot/dts/exynos5440.dtsi | 2 + > drivers/pci/host/Makefile | 3 +- > drivers/pci/host/pci-exynos.c | 530 ++++++++++ > drivers/pci/host/pcie-designware.c | 1011 ++++++-------------- > drivers/pci/host/pcie-designware.h | 65 ++ > 6 files changed, 874 insertions(+), 740 deletions(-) > create mode 100644 drivers/pci/host/pci-exynos.c > create mode 100644 drivers/pci/host/pcie-designware.h