From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sunyoung Kang Subject: RE: [PATCH RESEND v2 1/2] ARM: EXYNOS: Add clock support for Gscaler Date: Wed, 18 Jul 2012 17:44:33 +0900 Message-ID: <005401cd64c1$8e299d10$aa7cd730$%kang@samsung.com> References: <1342416803-30809-1-git-send-email-shaik.ameer@samsung.com> <1342416803-30809-2-git-send-email-shaik.ameer@samsung.com> <143701cd63a3$c0b81140$422833c0$%kim@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-path: Received: from mailout3.samsung.com ([203.254.224.33]:62884 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751275Ab2GRIog (ORCPT ); Wed, 18 Jul 2012 04:44:36 -0400 Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7C00FS0LM2GRB0@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 18 Jul 2012 17:44:34 +0900 (KST) Received: from NOSY0816KAN01 ([12.23.119.130]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7C008DPLM90R90@mmp1.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 18 Jul 2012 17:44:34 +0900 (KST) In-reply-to: <143701cd63a3$c0b81140$422833c0$%kim@samsung.com> Content-language: ko Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: 'Kukjin Kim' , 'Shaik Ameer Basha' , linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org Cc: olofj@google.com, thomas.ab@samsung.com, sylvester.nawrocki@gmail.com, sachin.kamat@linaro.org, joshi@samsung.com, ameersk@gmail.com Kukjin Kim wrote: > >Shaik Ameer Basha wrote: >> >> Add required clock support for Gscaler for exynos5 >> >Hi, > >Cc'ed Sunyoung Kang who knows gscaler well in my team. > >> Signed-off-by: Abhilash Kesavan >> Signed-off-by: Leela Krishna Amudala >> Signed-off-by: Prathyush K >> Signed-off-by: Shaik Ameer Basha >> --- >> arch/arm/mach-exynos/clock-exynos5.c | 79 >> ++++++++++++++++++++++++++++++++++ >> 1 files changed, 79 insertions(+), 0 deletions(-) >> >> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach- >> exynos/clock-exynos5.c >> index fefa336..c8293a3 100644 >> --- a/arch/arm/mach-exynos/clock-exynos5.c >> +++ b/arch/arm/mach-exynos/clock-exynos5.c >> @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = { >> .enable = exynos5_clk_ip_peric_ctrl, >> .ctrlbit = (1 << 14), >> }, { >> + .name = "gscl", >> + .devname = "exynos-gsc.0", >> + .enable = exynos5_clk_ip_gscl_ctrl, >> + .ctrlbit = (1 << 0), > >Sunyoung, I've seen (1 << 15) | (1 << 0) here instead, which one is right? > Actually, the ctrl bit, (1 << 0) is correct. The 15th bit Kukjin said is used for another purpose. >[snip] > >I think, following part should be moved between > >--- >static struct clksrc_clk exynos5_clk_aclk_66 = { >[snip] >}; > ><<>> > >static struct clk exynos5_init_clocks_off[] = { >--- > >Please don't put your clock code without any checking the clock code. > > >> +/* For ACLK_300_gscl_mid */ >> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = { >> + .clk = { >> + .name = "mout_aclk_300_gscl_mid", >> + }, >> + .sources = &exynos5_clkset_aclk, >> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 }, >> +}; >> + >> +/* For ACLK_300_gscl */ >> +struct clk *exynos5_clkset_aclk_300_gscl_list[] = { >> + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, >> + [1] = &exynos5_clk_sclk_vpll.clk, > >As I know, this is wrong. Its [1] should be >&exynos5_clk_mout_aclk_300_gscl_mid1.clk > Yes, right. It should be 'exynos5_clk_mout_aclk_300_gscl_mid1.clk' which is generated by CPLL. The VPLL shouldn't be used here. It means you need to implement CPLL for gscaler. As a note, CPLL can be used for fimd as well. [snip] Thanks. BRs Sunyoung