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[188.155.177.222]) by smtp.gmail.com with ESMTPSA id og37sm2584474ejc.100.2021.06.21.01.51.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Jun 2021 01:51:54 -0700 (PDT) Subject: Re: [PATCH 2/2] arm64: dts: exynos5433: Add cpu cache information To: Alim Akhtar , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org Cc: linux-samsung-soc@vger.kernel.org References: <20210617113739.66911-1-alim.akhtar@samsung.com> <20210617113739.66911-2-alim.akhtar@samsung.com> From: Krzysztof Kozlowski Message-ID: <0120db2f-e25e-a4ae-669b-a404dbfae05b@canonical.com> Date: Mon, 21 Jun 2021 10:51:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210617113739.66911-2-alim.akhtar@samsung.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On 17/06/2021 13:37, Alim Akhtar wrote: > This patch adds cpu caches information to its dt > nodes so that the same is available to userspace > via sysfs. > This SoC has 48/32 KB I/D cache for each A57 cores > with 2MB L2 cache. > And 32/32 KB I/D cache for each A53 cores with > 256KB L2 cache. > > Signed-off-by: Alim Akhtar > --- > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70 ++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > index 18a912eee360..8183a59e9046 100644 > --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > @@ -62,6 +62,13 @@ > clock-names = "apolloclk"; > operating-points-v2 = <&cluster_a53_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&apollo_l2>; > }; > > cpu1: cpu@101 { > @@ -72,6 +79,13 @@ > clock-frequency = <1300000000>; > operating-points-v2 = <&cluster_a53_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&apollo_l2>; > }; > > cpu2: cpu@102 { > @@ -82,6 +96,13 @@ > clock-frequency = <1300000000>; > operating-points-v2 = <&cluster_a53_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&apollo_l2>; > }; > > cpu3: cpu@103 { > @@ -92,6 +113,13 @@ > clock-frequency = <1300000000>; > operating-points-v2 = <&cluster_a53_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&apollo_l2>; > }; > > cpu4: cpu@0 { > @@ -104,6 +132,13 @@ > clock-names = "atlasclk"; > operating-points-v2 = <&cluster_a57_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0xc000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&atlas_l2>; > }; > > cpu5: cpu@1 { > @@ -114,6 +149,13 @@ > clock-frequency = <1900000000>; > operating-points-v2 = <&cluster_a57_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0xc000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&atlas_l2>; > }; > > cpu6: cpu@2 { > @@ -124,6 +166,13 @@ > clock-frequency = <1900000000>; > operating-points-v2 = <&cluster_a57_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0xc000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&atlas_l2>; > }; > > cpu7: cpu@3 { > @@ -134,6 +183,27 @@ > clock-frequency = <1900000000>; > operating-points-v2 = <&cluster_a57_opp_table>; > #cooling-cells = <2>; > + i-cache-size = <0xc000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&atlas_l2>; > + }; > + > + atlas_l2: l2-cache0 { Few other nodes (PMU, OPP tables) use a57/a53 names instead of codenames, so I would prefer to stay with them (so cluster_a57_l2). For Exynos7 it's fine as it uses Atlas already in labels. > + compatible = "cache"; > + cache-size = <0x200000>; > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + > + apollo_l2: l2-cache1 { > + compatible = "cache"; > + cache-size = <0x40000>; > + cache-line-size = <64>; > + cache-sets = <256>; > }; > }; > > Best regards, Krzysztof