From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kukjin Kim Subject: RE: [PATCH] arm: dts: exynos5: Remove multi core timer Date: Wed, 04 Jun 2014 10:45:14 +0900 Message-ID: <025401cf7f96$a1193740$e34ba5c0$@samsung.com> References: <1400188079-21832-1-git-send-email-chirantan@chromium.org> <53752E25.9060604@gmail.com> <53753443.8010303@gmail.com> <53753C17.1090002@gmail.com> <53754CE2.3000905@gmail.com> <033a01cf74f2$d025ce80$70716b80$@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-path: Received: from mailout2.samsung.com ([203.254.224.25]:37124 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752170AbaFDBpQ (ORCPT ); Tue, 3 Jun 2014 21:45:16 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N6M004U9FJEE470@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 04 Jun 2014 10:45:14 +0900 (KST) In-reply-to: Content-language: ko Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: 'Chirantan Ekbote' Cc: 'Sonny Rao' , 'Doug Anderson' , 'Tomasz Figa' , 'David Riley' , 'Russell King' , 'Olof Johansson' , linux-arm-kernel@lists.infradead.org, 'linux-samsung-soc' Chirantan Ekbote wrote: > > Hi Kukjin, > Hi, > On Wed, May 21, 2014 at 5:47 AM, Kukjin Kim wrote: > > Yeah, actually we don't need to reset the count value after suspend/resume. > > So, how about following? I think, it should be fine to you. > > > > diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c > > index 8d64200..d24db6f 100644 > > --- a/drivers/clocksource/exynos_mct.c > > +++ b/drivers/clocksource/exynos_mct.c > > @@ -157,12 +157,15 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo) > > { > > u32 reg; > > > > - exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); > > - exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); > > - > > reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); > > - reg |= MCT_G_TCON_START; > > - exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); > > + > > + if (!(reg & MCT_G_TCON_START)) { > > + exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); > > + exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); > > + > > + reg |= MCT_G_TCON_START; > > + exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); > > + } > > } > > > > > > As Doug mentioned, this seems more complicated than necessary since > the kernel doesn't care about the initial value of the mct counter at > all. Is there some reason from a hardware standpoint that the counter > needs to be cleared? If not, I would rather just delete the two > offending lines. I am sending a patch that does this instead. > So decision point is that the initialization of MCT counter is required or not when kernel begins. Yes it doesn't matter, basically MCT start has no problem with any initial value and additionally its hardware reset value is 0x0. OK, your suggestion is fair enough. Thanks, Kukjin