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Wed, 29 Jul 2026 05:12:50 +0000 (GMT) From: "Alim Akhtar" To: "'Alexandru Chimac'" , "'Krzysztof Kozlowski'" , "'Sylwester Nawrocki'" , "'Chanwoo Choi'" , "'Peter Griffin'" , "'Michael Turquette'" , "'Stephen Boyd'" , "'Brian Masney'" , "'Rob Herring'" , "'Conor Dooley'" , "'Krzysztof Kozlowski'" Cc: , , , , In-Reply-To: <20260722-exynos9610-clocks-v3-3-c672a2a30889@chimac.ro> Subject: RE: [PATCH v3 3/5] clk: samsung: clk-pll: Add support for pll_1061x Date: Wed, 29 Jul 2026 10:42:49 +0530 Message-ID: <07e101dd1f18$e83ab2a0$b8b017e0$@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQHTw+ptVoCYShTtVq94NkBsvgZUugKcCweMAdasPym2cxLvQA== Content-Language: en-us X-CMS-MailID: 20260729051253epcas5p13c6aaadd8335f3a07aba4f2e53cc10c5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260722204419epcas5p4199c800b0a94ff523f0e9e9c5aaeeaba References: <20260722-exynos9610-clocks-v3-0-c672a2a30889@chimac.ro> <20260722-exynos9610-clocks-v3-3-c672a2a30889@chimac.ro> Hi Alexandru > -----Original Message----- > From: Alexandru Chimac > Sent: Thursday, July 23, 2026 2:14 AM > To: Krzysztof Kozlowski ; Sylwester Nawrocki > ; Chanwoo Choi ; > Peter Griffin ; Alim Akhtar > ; Michael Turquette > ; Stephen Boyd ; Brian > Masney ; Rob Herring ; Conor > Dooley ; Alexandru Chimac ; > Krzysztof Kozlowski > Cc: linux-samsung-soc=40vger.kernel.org; linux-clk=40vger.kernel.org; > devicetree=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; lin= ux- > kernel=40vger.kernel.org > Subject: =5BPATCH v3 3/5=5D clk: samsung: clk-pll: Add support for pll_10= 61x >=20 > These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and are simil= ar > to pll_1460x (using CON3 instead of CON1), so the code for that can handl= e > this PLL with a few small adaptations. >=20 It is good to mention that PLL_1061x is a fractional type PLL and used to s= upply BLK_MMC and AUD, atleast on 9610 SoC > Signed-off-by: Alexandru Chimac > --- > drivers/clk/samsung/clk-pll.c =7C 29 ++++++++++++++++++++++------- > drivers/clk/samsung/clk-pll.h =7C 1 + > 2 files changed, 23 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.= c index > e74552846ba3..2cda87235fa2 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > =40=40 -781,15 +781,20 =40=40 static unsigned long > samsung_pll46xx_recalc_rate(struct clk_hw *hw, > u64 fvco =3D parent_rate; >=20 > pll_con0 =3D readl_relaxed(pll->con_reg); > - pll_con1 =3D readl_relaxed(pll->con_reg + 4); > - mdiv =3D (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type =3D=3D > pll_1460x) ? > + if (pll->type =3D=3D pll_1061x) > + pll_con1 =3D readl_relaxed(pll->con_reg + 0xc); Actually this is PLL_CON3 in UM, not suggesting to use a new variable but a= comment here will help.=20 Thanks=21