From mboxrd@z Thu Jan 1 00:00:00 1970 From: Krzysztof Kozlowski Subject: Re: [PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated Date: Tue, 09 Dec 2014 13:59:42 +0100 Message-ID: <1418129982.19339.6.camel@AMDC1943> References: <1417788934-23447-1-git-send-email-k.kozlowski@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from mailout3.w1.samsung.com ([210.118.77.13]:60359 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932197AbaLIM7r (ORCPT ); Tue, 9 Dec 2014 07:59:47 -0500 In-reply-to: <1417788934-23447-1-git-send-email-k.kozlowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Sylwester Nawrocki Cc: Tomasz Figa , Mike Turquette , Stephen Boyd , Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kevin Hilman , Javier Martinez Canillas , Kyungmin Park , Marek Szyprowski , Bartlomiej Zolnierkiewicz On pi=C4=85, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote: > Audio subsystem clocks are located in separate block. On Exynos 5420 = if > clock for this block (from main clock domain) 'mau_epll' is gated the= n > any read or write to audss registers will block. >=20 > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit > after introducing runtime PM to pl330 DMA driver. After that commit t= he > 'mau_epll' was gated, because the "amba" clock was disabled and there > were no more users of mau_epll. >=20 > The system hang on one of steps: > 1. Disabling unused clocks from audss block. > 2. During audss GPIO setup (just before probing i2s0 because > samsung_pinmux_setup() tried to access memory from audss block whi= ch was > gated. >=20 > Add a workaround for this by enabling the 'mau_epll' clock in probe. >=20 > Signed-off-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++= ++++- > 1 file changed, 28 insertions(+), 1 deletion(-) Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated). This is a non-intrusive workaround for that issue, as wanted by Sylwester: https://lkml.org/lkml/2014/12/5/223 Any comments on this? Best regards, Krzysztof > diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/sam= sung/clk-exynos-audss.c > index acce708ace18..0916a81fa932 100644 > --- a/drivers/clk/samsung/clk-exynos-audss.c > +++ b/drivers/clk/samsung/clk-exynos-audss.c > @@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock); > static struct clk **clk_table; > static void __iomem *reg_base; > static struct clk_onecell_data clk_data; > +/* > + * On Exynos5420 this will be a clock which has to be enabled before= any > + * access to audss registers. Typically a child of EPLL. > + * > + * On other platforms this will be -ENODEV. > + */ > +static struct clk *epll; > =20 > #define ASS_CLK_SRC 0x0 > #define ASS_CLK_DIV 0x4 > @@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_= device *pdev) > dev_err(&pdev->dev, "failed to map audss registers\n"); > return PTR_ERR(reg_base); > } > + /* EPLL don't have to be enabled for boards other than Exynos5420 *= / > + epll =3D ERR_PTR(-ENODEV); > =20 > clk_table =3D devm_kzalloc(&pdev->dev, > sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, > @@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platfor= m_device *pdev) > pll_in =3D devm_clk_get(&pdev->dev, "pll_in"); > if (!IS_ERR(pll_ref)) > mout_audss_p[0] =3D __clk_get_name(pll_ref); > - if (!IS_ERR(pll_in)) > + if (!IS_ERR(pll_in)) { > mout_audss_p[1] =3D __clk_get_name(pll_in); > + > + if (variant =3D=3D TYPE_EXYNOS5420) { > + epll =3D pll_in; > + > + ret =3D clk_prepare_enable(epll); > + if (ret) { > + dev_err(&pdev->dev, > + "failed to prepare the epll clock\n"); > + return ret; > + } > + } > + } > clk_table[EXYNOS_MOUT_AUDSS] =3D clk_register_mux(NULL, "mout_audss= ", > mout_audss_p, ARRAY_SIZE(mout_audss_p), > CLK_SET_RATE_NO_REPARENT, > @@ -203,6 +224,9 @@ unregister: > clk_unregister(clk_table[i]); > } > =20 > + if (!IS_ERR(epll)) > + clk_disable_unprepare(epll); > + > return ret; > } > =20 > @@ -217,6 +241,9 @@ static int exynos_audss_clk_remove(struct platfor= m_device *pdev) > clk_unregister(clk_table[i]); > } > =20 > + if (!IS_ERR(epll)) > + clk_disable_unprepare(epll); > + > return 0; > } > =20