From mboxrd@z Thu Jan 1 00:00:00 1970 From: Russell King - ARM Linux Subject: Re: [PATCH 0/40] Complete set of clocksource/sched_clock patches Date: Sun, 19 Dec 2010 14:49:50 +0000 Message-ID: <20101219144950.GH3047@n2100.arm.linux.org.uk> References: <20101217113223.GC9937@n2100.arm.linux.org.uk> <19725.57447.256528.883703@pilspetsen.it.uu.se> <20101219105209.GN9937@n2100.arm.linux.org.uk> <19725.64412.395353.947407@pilspetsen.it.uu.se> <20101219125508.GG3047@n2100.arm.linux.org.uk> <19726.4420.289089.490319@pilspetsen.it.uu.se> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <19726.4420.289089.490319@pilspetsen.it.uu.se> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Mikael Pettersson Cc: Viresh Kumar , Kevin Hilman , Lennert Buytenhek , linux-samsung-soc@vger.kernel.org, "Hans J. Koch" , Scott Branden , Tony Lindgren , David Brown , Alessandro Rubini , Jiandong Zheng , Wan ZongShun , linux-arm-msm@vger.kernel.org, STEricsson , Kukjin Kim , linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Walker , Eric Miao , Linus Walleij , Erik Gilling , Nicolas Pitre , Bryan Huntsman Sascha Hauer List-Id: linux-samsung-soc@vger.kernel.org On Sun, Dec 19, 2010 at 03:05:56PM +0100, Mikael Pettersson wrote: > tmr = timer mode register > tcr = timer counter register > trr = timer reload register > > When a timer is in periodic mode it reloads itself from its reload > register when the counter register decrements to zero. Ok. > > Does trr need to be written in > > ->set_mode (if so that's another bug in this code)? > > trr{0,1} need not and should not be changed after iop_time_init(). It sounds like trr0 needs to be written in ->set_mode's CLOCK_EVT_MODE_PERIODIC path then, because with my patch, we never set this register. Or will trr0 be updated when we write tcr0 ?