From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Boxer Subject: Re: [PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos SoCs Date: Tue, 6 Aug 2013 11:21:08 -0500 Message-ID: <3BCA86D7-5A34-418E-A468-F7DF62FD1592@gmail.com> References: <003c01ce89f3$3abc4bc0$b034e340$@samsung.com> <27536111.odlCO093Zi@amdc1032> <003c01ce91cd$427fad70$c77f0850$@samsung.com> <1429191.3FDem6vW0S@amdc1032> <002001ce928a$f5a7f390$e0f7dab0$@samsung.com> <5200F781.9020300@samsung.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============6564920032234426117==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Cc: Linux Samsung SOC , Hyunwoong Kim , Bartlomiej Zolnierkiewicz , Sachin Kamat , Prathyush , Subash Patel , Linux Kernel , Keyyoung Park , Rahul Sharma , Grant Grundler , Linux IOMMU , Kukjin Kim , Antonios Motakis , Cho KyongHo , kvmarm , Linux ARM Kernel List-Id: linux-samsung-soc@vger.kernel.org --===============6564920032234426117== Content-Type: multipart/alternative; boundary="52012274_625558ec_13e" --52012274_625558ec_13e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ok =20 ---Sent from Boxer =7C http://getboxer.com Hi Marek, On Tue, Aug 6, 2013 at 6:17 AM, Marek Szyprowski wrote: ... > IMHO it is much better to have a simple driver, which binds to a single= > IOMMU controller and leave it to the driver whether to have a same virt= ual address > space for all parts of =46IMC-IS or M=46C submodules/memory ports or no= t. I understand this part. I having written the IOMMU support for 4 different IOMMUs, all of which had exactly one IO Page Table and one IOMMU shared by many devices. > Just make sure that it will be possible to attach more than one sysmmu = > controller to one iommu domain. I don't understand how this is possible. Can someone explain this better in the IOMMU documentation please=3F =22iommu domain=22 to me means one virtual IO address space for attached = devices that can master DMA transactions. The IOMMU then uses it's IO Page Table to translate the DMA address to the system physical address space and forwards the transaction. What is the role of the sysmmu in all of this=3F Is the sysmmu just the MMU (or collection of MMU) for host DRAM=3F Or is sysmmu responsible for =22other stuff=22=3F (clocks, power domains,= MMU, etc) I can understand we might have multiple MMUs in a system...e.g. every range of memory might have it's own MMU. But they share the same physical address space and generally live under one page table. Because of =22one page table=22 I would consider them one entity from the= the IOMMUs perspective. thanks, grant -- To unsubscribe from this list: send the line =22unsubscribe linux-kernel=22= in the body of a message to majordomo=40vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the =46AQ at http://www.tux.org/lkml/ --52012274_625558ec_13e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ok

---
Sent from Boxer =7C http://getboxer.com
On Tue, Aug 06, 2013 at 1= 1:07 AM, Grant Grundler wrote:
Hi Marek,

On Tue, Aug 6, 2013 at 6:17 AM, Ma= rek Szyprowski
wrote:
...
> IMHO= it is much better to have a simple driver, which binds to a single
&g= t; IOMMU controller and leave it to the driver whether to have a same vir= tual address
> space for all parts of =46IMC-IS or M=46C submodules= /memory ports or not.

I understand this part. I having written the= IOMMU support for 4
different IOMMUs, all of which had exactly one IO= Page Table and one
IOMMU shared by many devices.

> Just mak= e sure that it will be possible to attach more than one sysmmu
> co= ntroller to one iommu domain.

I don't understand how this is possi= ble. Can someone explain this
better in the IOMMU documentation please= =3F

=22iommu domain=22 to me means one virtual IO address space fo= r attached
devices that can master DMA transactions. The IOMMU then us= es it's IO
Page Table to translate the DMA address to the system physi= cal address
space and forwards the transaction.

What is the rol= e of the sysmmu in all of this=3F
Is the sysmmu just the MMU (or colle= ction of MMU) for host DRAM=3F
Or is sysmmu responsible for =22other s= tuff=22=3F (clocks, power domains, MMU, etc)

I can understand we m= ight have multiple MMUs in a system...e.g. every
range of memory might= have it's own MMU. But they share the same
physical address space and= generally live under one page table.
Because of =22one page table=22 = I would consider them one entity from the
the IOMMUs perspective.
<= br>thanks,
grant
--
To unsubscribe from this list: send the line= =22unsubscribe linux-kernel=22 in
the body of a message to majordomo=40= vger.kernel.org
More majordomo info at http://vger.kernel.org/majordo= mo-info.html
Please read the =46AQ at http://www.tux.org/lkml/
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