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Wed, 6 Aug 2025 05:46:12 +0000 (GMT) From: "Alim Akhtar" To: "'Manivannan Sadhasivam'" Cc: "'Konrad Dybcio'" , "'Krzysztof Kozlowski'" , "'Ram Kumar Dwivedi'" , , , , , , , , , , , , , , In-Reply-To: Subject: RE: [PATCH 2/3] arm64: dts: qcom: sa8155: Add gear and rate limit properties to UFS Date: Wed, 6 Aug 2025 11:16:11 +0530 Message-ID: <06f301dc0695$6bf25690$43d703b0$@samsung.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQKnlt0Ez4U7OU6i7DDtpxZiPKvKiQEsJt2OAdY+bWECqijPQgIPv58TAQlCtSUCbRSB8gJXYzfzAduHMkYBp6Y8EQJl+KeTsiJiETA= X-CMS-MailID: 20250806054614epcas5p3407494fd3bf0360c722af9c7c6ada6c5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250805170638epcas5p4cb0cc78c5b5d77072cec547380b9f03d References: <061b01dc062d$25c47800$714d6800$@samsung.com> <061c01dc062f$70ec34b0$52c49e10$@samsung.com> <87c37d65-5ab1-4443-a428-dc3592062cdc@oss.qualcomm.com> <061d01dc0631$c1766c00$44634400$@samsung.com> <3cd33dce-f6b9-4f60-8cb2-a3bf2942a1e5@oss.qualcomm.com> <06d201dc0689$9f438200$ddca8600$@samsung.com> > -----Original Message----- > From: 'Manivannan Sadhasivam' > Sent: Wednesday, August 6, 2025 10:35 AM > To: Alim Akhtar > Cc: 'Konrad Dybcio' ; 'Krzysztof > Kozlowski' ; 'Ram Kumar Dwivedi' > ; avri.altman=40wdc.com; > bvanassche=40acm.org; robh=40kernel.org; krzk+dt=40kernel.org; > conor+dt=40kernel.org; andersson=40kernel.org; konradybcio=40kernel.org; > James.Bottomley=40hansenpartnership.com; martin.petersen=40oracle.com; > agross=40kernel.org; linux-arm-msm=40vger.kernel.org; linux- > scsi=40vger.kernel.org; devicetree=40vger.kernel.org; linux- > kernel=40vger.kernel.org > Subject: Re: =5BPATCH 2/3=5D arm64: dts: qcom: sa8155: Add gear and rate = limit > properties to UFS >=20 > On Wed, Aug 06, 2025 at 09:51:43AM GMT, Alim Akhtar wrote: >=20 > =5B...=5D >=20 > > > >> Introducing generic solutions preemptively for problems that are > > > >> simple in concept and can occur widely is good practice (although > > > >> it's sometimes hard to gauge whether this is a one-off), as if > > > >> the issue spreads a generic solution will appear at some point, > > > >> but we'll have to keep supporting the odd ones as well > > > >> > > > > Ok, > > > > I would prefer if we add a property which sounds like =22poor > > > > thermal dissipation=22 or =22routing channel loss=22 rather than ad= ding > > > > limiting UFS gear > > > properties. > > > > Poor thermal design or channel losses are generic enough and can > > > > happen > > > on any board. > > > > > > This is exactly what I'm trying to avoid through my suggestion - one > > > board may have poor thermal dissipation, another may have channel > > > losses, yet another one may feature a special batch of UFS chips > > > that will set the world on fire if instructed to attempt link > > > training at gear 7 - they all are causes, as opposed to describing > > > what needs to happen (i.e. what the hardware must be treated as - > > > gear N incapable despite what can be discovered at runtime), with > > > perhaps a comment on the side > > > > > But the solution for all possible board problems can't be by limiting G= ear > speed. >=20 > Devicetree properties should precisely reflect how they are relevant to t= he > hardware. 'limiting-gear-speed' is self-explanatory that the gear speed i= s > getting limited (for a reason), but the devicetree doesn't need to descri= be > the > *reason* itself. >=20 > > So it should be known why one particular board need to limit the gear. >=20 > That goes into the description, not in the property name. >=20 > > I understand that this is a static configuration, where it is already k= nown > that board is broken for higher Gear. > > Can this be achieved by limiting the clock? If not, can we add a board > specific _quirk_ and let the _quirk_ to be enabled from vendor specific > hooks? > > >=20 > How can we limit the clock without limiting the gears? When we limit the > gear/mode, both clock and power are implicitly limited. >=20 Possibly someone need to check with designer of the SoC if that is possible= or not. Did we already tried _quirk_? If not, why not?=20 If the board is so poorly designed and can't take care of the channel loses= or heat dissipation etc, Then I assumed the gear negotiation between host and device should fail for= the higher gear=20 and driver can have a re-try logic to re-init / re-try =22power mode change= =22 at the lower gear. Is that not possible / feasible? > - Mani >=20 > -- > =E0=AE=AE=E0=AE=A3=E0=AE=BF=E0=AE=B5=E0=AE=A3=E0=AF=8D=E0=AE=A3=E0=AE=A9= =E0=AF=8D=20=E0=AE=9A=E0=AE=A4=E0=AE=BE=E0=AE=9A=E0=AE=BF=E0=AE=B5=E0=AE=AE= =E0=AF=8D=0D=0A=0D=0A