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Thu, 7 Aug 2025 16:38:33 +0000 (GMT) From: "Alim Akhtar" To: "'Manivannan Sadhasivam'" Cc: "'Konrad Dybcio'" , "'Krzysztof Kozlowski'" , "'Ram Kumar Dwivedi'" , , , , , , , , , , , , , , In-Reply-To: Subject: RE: [PATCH 2/3] arm64: dts: qcom: sa8155: Add gear and rate limit properties to UFS Date: Thu, 7 Aug 2025 22:08:32 +0530 Message-ID: <0d6801dc07b9$b869adf0$293d09d0$@samsung.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQHWPm1h7sMntUE9BjOfqFdL0FvwlQKqKM9CAg+/nxMBCUK1JQJtFIHyAldjN/MB24cyRgGnpjwRAmX4p5MB936htgLh1QaLARPOx0SzsAOLcA== X-CMS-MailID: 20250807163836epcas5p15300402e991a5be93922a414f2bd3959 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250806112542epcas5p15f2fdea9b635a43c54885dbdffa03b60 References: <061b01dc062d$25c47800$714d6800$@samsung.com> <061c01dc062f$70ec34b0$52c49e10$@samsung.com> <87c37d65-5ab1-4443-a428-dc3592062cdc@oss.qualcomm.com> <061d01dc0631$c1766c00$44634400$@samsung.com> <3cd33dce-f6b9-4f60-8cb2-a3bf2942a1e5@oss.qualcomm.com> <06d201dc0689$9f438200$ddca8600$@samsung.com> <06f301dc0695$6bf25690$43d703b0$@samsung.com> > -----Original Message----- > From: 'Manivannan Sadhasivam' > Sent: Wednesday, August 6, 2025 4:56 PM > To: Alim Akhtar > Cc: 'Konrad Dybcio' ; 'Krzysztof =5B...=5D > > > > > > On Wed, Aug 06, 2025 at 09:51:43AM GMT, Alim Akhtar wrote: > > > > > > =5B...=5D > > > > > > > > >> Introducing generic solutions preemptively for problems that > > > > > >> are simple in concept and can occur widely is good practice > > > > > >> (although it's sometimes hard to gauge whether this is a > > > > > >> one-off), as if the issue spreads a generic solution will > > > > > >> appear at some point, but we'll have to keep supporting the > > > > > >> odd ones as well > > > > > >> > > > > > > Ok, > > > > > > I would prefer if we add a property which sounds like =22poor > > > > > > thermal dissipation=22 or =22routing channel loss=22 rather tha= n > > > > > > adding limiting UFS gear > > > > > properties. > > > > > > Poor thermal design or channel losses are generic enough and > > > > > > can happen > > > > > on any board. > > > > > > > > > > This is exactly what I'm trying to avoid through my suggestion - > > > > > one board may have poor thermal dissipation, another may have > > > > > channel losses, yet another one may feature a special batch of > > > > > UFS chips that will set the world on fire if instructed to > > > > > attempt link training at gear 7 - they all are causes, as > > > > > opposed to describing what needs to happen (i.e. what the > > > > > hardware must be treated as - gear N incapable despite what can > > > > > be discovered at runtime), with perhaps a comment on the side > > > > > > > > > But the solution for all possible board problems can't be by > > > > limiting Gear > > > speed. > > > > > > Devicetree properties should precisely reflect how they are relevant > > > to the hardware. 'limiting-gear-speed' is self-explanatory that the > > > gear speed is getting limited (for a reason), but the devicetree > > > doesn't need to describe the > > > *reason* itself. > > > > > > > So it should be known why one particular board need to limit the ge= ar. > > > > > > That goes into the description, not in the property name. > > > > > > > I understand that this is a static configuration, where it is > > > > already known > > > that board is broken for higher Gear. > > > > Can this be achieved by limiting the clock? If not, can we add a > > > > board > > > specific _quirk_ and let the _quirk_ to be enabled from vendor > > > specific hooks? > > > > > > > > > > How can we limit the clock without limiting the gears? When we limit > > > the gear/mode, both clock and power are implicitly limited. > > > > > Possibly someone need to check with designer of the SoC if that is poss= ible > or not. >=20 > It's not just clock. We need to consider reducing regulator, interconnect > votes also. But as I said above, limiting the gear/mode will take care of= all > these parameters. >=20 > > Did we already tried _quirk_? If not, why not? > > If the board is so poorly designed and can't take care of the channel > > loses or heat dissipation etc, Then I assumed the gear negotiation > > between host and device should fail for the higher gear and driver can = have > a re-try logic to re-init / re-try =22power mode change=22 at the lower g= ear. Is > that not possible / feasible? > > >=20 > I don't see why we need to add extra logic in the UFS driver if we can ex= tract > that information from DT. >=20 You didn=E2=80=99t=20answer=20my=20question=20entirely,=20I=20am=20still=20= not=20able=20to=20visualised=20how=20come=20Linkup=20is=20happening=20in=20= higher=20gear=20and=20then=20=0D=0ASuddenly=20it=20is=20failing=20and=20we= =20need=20to=20reduce=20the=20gear=20to=20solve=20that?=0D=0AThat's=20why= =20my=20suggestion=20is=20to=20go=20for=20a=20re-try=20at=20lower=20gear=20= when=20problem=20happens.=0D=0AIt=20is=20not=20that=20since=20adding=20DT= =20property=20is=20simple=20to=20just=20go=20that=20path,=20that=20is=20sol= ving=20_just_=20this=20case,=20may=20be.=20=0D=0A=0D=0A=0D=0A=0D=0A>=20-=20= Mani=0D=0A>=20=0D=0A>=20--=0D=0A>=20=E0=AE=AE=E0=AE=A3=E0=AE=BF=E0=AE=B5=E0= =AE=A3=E0=AF=8D=E0=AE=A3=E0=AE=A9=E0=AF=8D=20=E0=AE=9A=E0=AE=A4=E0=AE=BE=E0= =AE=9A=E0=AE=BF=E0=AE=B5=E0=AE=AE=E0=AF=8D=0D=0A=0D=0A