Re: Control Mode page (0xA) QERR bit setting

[James Bottomley <James.Bottomley@SteelEye.com>]

On Mon, 2004-08-30 at 22:45, Jeremy Higdon wrote:
> It looks as though the midlayer assumes that QERR is 0.  Is that correct?

Actually, no, the mid-layer is agnostic to the setting of QERR.  On
error, it simply quiesces the host and waits for all the commands to
timeout or complete.

> If QERR is 0, then a check condition for one command will not affect other
> commands, whereas if QERR is 1, then when one command gets a check condition,
> all others for that ITL are silently aborted.

Yes, so we see them time out in the error handler.

> Since I wasn't able to find any code (other than in the ipr driver) that
> completed all outstanding commands to a Lun when a check condition is
> received, I figure that we depend on QERR=0.

No, we work for either.  QERR != 0 is very rare in mode pages, primarily
because it's almost impossible to predict what tags actually got dropped
on the floor because you don't know the status of the head scheduler
(only tasks accepted and scheduled behind the failing tag actually get
dropped; executing tasks ahead of it are allowed to complete as long as
the failing condition doesn't impact them).

James