Re: I/O write ordering

James Bottomley
2004-09-22T15:44:05Z

On Wed, 2004-09-22 at 11:28, Benjamin Herrenschmidt wrote:
> - consistent memory is either cacheable or non-cacheable depending on
> the CPU type (some embedded CPUs who don't implement cache coherency
> will map consistent memory as non-cacheable, most desktop CPUs and all
> 64 bits CPU don't mind and will map it cacheable).

Yes, this was what I feared, since streaming memory has exact ownership
and handoff paradigms for handling it.

Your problem case is consistent memory access vs readX/writeX then.

Could you not just make consistent memory always uncacheable ... then
you'd look identical to everyone else...

The alternative in I/O terms is to implement an ownership model for
consistent PCI memory itself...which is sort of what I had to do in the
dma_noncoherent_alloc() API, but to make that more general would be
quite a bit of work.

James