Re: SCSI QLA not working on latest *-mm SN2

Andrew Vasquez
2004-09-16T21:00:25Z

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On Thu, 2004-09-16 at 13:05, Jesse Barnes wrote:
> On Thursday, September 16, 2004 12:56 pm, Paul Jackson wrote:
> > Andrew Vasquez has been looking at this, via private email with just
> > me (no progress yet). Figured I update the larger list with this much ...
>
> It seems to be failing on one of the accesses to PCI_COMMAND in config space
> in qla2x00_reset_chip(). I'm checking now to see if we're accessing the card
> right after a reset but before the card has finished. That would cause a
> master abort, the symptom I'm seeing at least.
>

Interesting, the only changes in reset_chip() are for PCI posting
issues. Relevant diff attached.

--
Andrew

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diff -Nurdp -X dontdiff 80000b14/qla_init.c 80000b21/qla_init.c
--- 80000b14/qla_init.c 2004-06-23 17:12:33.000000000 -0700
+++ 80000b21/qla_init.c 2004-09-02 13:11:35.000000000 -0700
@@ -315,6 +317,7 @@ qla2x00_pci_config(scsi_qla_host_t *ha)

/* Select FPM registers. */
WRT_REG_WORD(&ha->iobase->ctrl_status, 0x20);
+ RD_REG_WORD(&ha->iobase->ctrl_status);

/* Get the fb rev level */
ha->fb_rev = RD_FB_CMD_REG(ha, ha->iobase);
@@ -324,6 +327,7 @@ qla2x00_pci_config(scsi_qla_host_t *ha)

/* Deselect FPM registers. */
WRT_REG_WORD(&ha->iobase->ctrl_status, 0x0);
+ RD_REG_WORD(&ha->iobase->ctrl_status);

/* Release RISC module. */
WRT_REG_WORD(&ha->iobase->hccr, HCCR_RELEASE_RISC);
@@ -417,25 +421,32 @@ qla2x00_reset_chip(scsi_qla_host_t *ha)
udelay(100);
}
} else {
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */
udelay(10);
}

/* Select FPM registers. */
WRT_REG_WORD(&reg->ctrl_status, 0x20);
+ RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */

/* FPM Soft Reset. */
WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
+ RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */

/* Toggle Fpm Reset. */
- if (!IS_QLA2200(ha))
+ if (!IS_QLA2200(ha)) {
WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
+ RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
+ }

/* Select frame buffer registers. */
WRT_REG_WORD(&reg->ctrl_status, 0x10);
+ RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */

/* Reset frame buffer FIFOs. */
if (IS_QLA2200(ha)) {
WRT_FB_CMD_REG(ha, reg, 0xa000);
+ RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
} else {
WRT_FB_CMD_REG(ha, reg, 0x00fc);

@@ -449,19 +460,25 @@ qla2x00_reset_chip(scsi_qla_host_t *ha)

/* Select RISC module registers. */
WRT_REG_WORD(&reg->ctrl_status, 0);
+ RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */

/* Reset RISC processor. */
WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */

/* Release RISC processor. */
WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */
}

WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */
WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */

/* Reset ISP chip. */
WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
+ RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */

/* Wait for RISC to recover from reset. */
if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
@@ -482,12 +499,13 @@ qla2x00_reset_chip(scsi_qla_host_t *ha)

/* Reset RISC processor. */
WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */

WRT_REG_WORD(&reg->semaphore, 0);

/* Release RISC processor. */
WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
- RD_REG_WORD(&reg->hccr); /* PCI Posting. */
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */

if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
for (cnt = 0; cnt < 30000; cnt++) {
@@ -516,8 +534,10 @@ qla2x00_reset_chip(scsi_qla_host_t *ha)
pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);

/* Disable RISC pause on FPM parity error. */
- if (!IS_QLA2100(ha))
+ if (!IS_QLA2100(ha)) {
WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */
+ }

spin_unlock_irqrestore(&ha->hardware_lock, flags);
}
@@ -548,6 +568,8 @@ qla2x00_chip_diag(scsi_qla_host_t *ha)

/* Reset ISP chip. */
WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
+ RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
+
/*
* We need to have a delay here since the card will not respond while
* in reset causing an MCA on some architectures.
@@ -568,7 +590,9 @@ qla2x00_chip_diag(scsi_qla_host_t *ha)

/* Reset RISC processor. */
WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */
WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
+ RD_REG_WORD(&reg->hccr); /* PCI Posting. */

/* Workaround for QLA2312 PCI parity error */
if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {