From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Bottomley Subject: Re: I/O write ordering Date: 22 Sep 2004 11:22:03 -0400 Sender: linux-scsi-owner@vger.kernel.org Message-ID: <1095866530.2295.8.camel@mulgrave> References: <1095789421.2467.414.camel@mulgrave> <200409211409.11095.jbarnes@engr.sgi.com> <20040921190625.GB11708@colo.lackof.org> <20040921210341.GC146363@sgi.com> <20040921211108.GA16153@parcelfarce.linux.theplanet.co.uk> <20040921214302.GG146363@sgi.com> <20040922000211.GE16153@parcelfarce.linux.theplanet.co.uk> <20040922011652.GD147856@sgi.com> <20040922014428.GD20053@colo.lackof.org> <20040922025805.GA148414@sgi.com> <20040922143208.GL16153@parcelfarce.linux.theplanet.co.uk> <1095864485.2143.1.camel@mulgrave> <1095864709.6297.5.camel@gaston> <1095865892.1715.5.camel@mulgrave> <1095865863.6340.7.camel@gaston> Mime-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-path: Received: from stat16.steeleye.com ([209.192.50.48]:54423 "EHLO hancock.sc.steeleye.com") by vger.kernel.org with ESMTP id S266137AbUIVPWZ (ORCPT ); Wed, 22 Sep 2004 11:22:25 -0400 In-Reply-To: <1095865863.6340.7.camel@gaston> List-Id: linux-scsi@vger.kernel.org To: Benjamin Herrenschmidt Cc: Matthew Wilcox , Jeremy Higdon , Grant Grundler , Jesse Barnes , Matthew Wilcox , Andrew Vasquez , pj@sgi.com, SCSI Mailing List , mdr@cthulhu.engr.sgi.com, jeremy@cthulhu.engr.sgi.com, djh@cthulhu.engr.sgi.com, Andrew Morton , Richard Henderson , Paul Mackerras On Wed, 2004-09-22 at 11:11, Benjamin Herrenschmidt wrote: > Set by the CPU as non-cacheable. I know that ... but that definition is architecture specific and not helpful. I mean when for I/O transactions does the CPU mark memory as uncacheable. Is it for the PCI spaces only or for consistent PCI memory as well? We need to ascertain in generic I/O terms exactly what it is that you want synchronising. James