From: Jeremy Higdon <jeremy@sgi.com>
To: linux-scsi@vger.kernel.org
Subject: Control Mode page (0xA) QERR bit setting
Date: Mon, 30 Aug 2004 19:45:20 -0700 [thread overview]
Message-ID: <20040831024520.GA2118@sgi.com> (raw)
It looks as though the midlayer assumes that QERR is 0. Is that correct?
If QERR is 0, then a check condition for one command will not affect other
commands, whereas if QERR is 1, then when one command gets a check condition,
all others for that ITL are silently aborted.
Since I wasn't able to find any code (other than in the ipr driver) that
completed all outstanding commands to a Lun when a check condition is
received, I figure that we depend on QERR=0.
thanks
jeremy
next reply other threads:[~2004-08-31 2:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-08-31 2:45 Jeremy Higdon [this message]
2004-08-31 3:33 ` Control Mode page (0xA) QERR bit setting James Bottomley
2004-08-31 4:48 ` Jeremy Higdon
2004-08-31 13:55 ` Brian King
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